Thomas C. Holloway

An 0.8µm CMOS technology for high performance logic applications

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

VLSI Local interconnect level using titanium nitride

A local interconnect technology has been developed for VLSI CMOS applications using a titanium nitride layer. The technology has been realized by utilizing the titanium nitride layer that forms during the self-aligned titanium silicide process: which is used to simultanously reduce gate and junction sheet resistances to < 1 ohm/sq. Normally the TiN layer is discarded, but in this process the 0.1µm thick TiN layer is patterned and etched to provide local connections between gates and N+ and P+ junctions, with a sheet resistance of < 10 ohm/sq. This is accomplished without area consuming contacts or metal straps, and without any additional deposition steps, in addition to providing a VLSI version of the buried contact process, the technology results in self-aligned contacts and minimum geometry junctions, for reduced capacitance. The technology has been demonstrated by the fabrication of a CMOS VLSI memory with nearly half a million 1µm transistors.

Reliability design of p/sup +/-pocket implant LDD transistors

It is shown that the reliability design of p/sup +/-pocket LDD (lightly doped drain) transistors is dependent on the pocket implant energy, which controls the positions of the peak field and breakdown regions. A optimum of 60 keV implant in this example gives fairly good ESD (electrostatic discharge) reliability and excellent hot carrier immunity, while preventing transistor punchthrough effects. It is also shown that it is the electric field gradient at the surface rather than the substrate current level that can have a major impact on hot carrier degradation. In fact, for future VLSI transistors this technique can be used to improve the hot carrier reliability. Finally, further insight into the poor ESD performance of LDD transistors is obtained which indicates that the junction breakdown design is important for the ESD performance of LDD or DDD (double diffused drain) transistors.<<ETX>>

A standby current limited performance figure of merit for deep sub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM/sub max/. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM/sub max/ technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM/sub max/ methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM/sub max/. The value of gate length at which FOM/sub max/ occurs decreases with decreasing supply voltage. FOM/sub max/ analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm.

The Hi-C RAM cell concept

An MOS dynamic RAM cell concept called the High Capacity (Hi-C) RAM Cell which combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DLP) structure is described. Analytically, the Hi-C cell is predicted to have a charge storage capcity per unit area 50 - 100% greater than that of the regular 1-T or DLP cells, and a leakage current lower than that of the 1-T and DLP cells. Results of measurements on the first test structures show a 45 - 80% increase in charge capacity and up to 3X reduction in leakage current. In addition, the implant doses required to fabricate the Hi-C cell can be conveniently chosen so that the charge capacity is both maximized and independent of the n-type implant dose in the storage region.

A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

The authors describe a 0.5- mu m BiCMOS technology for high-performance logic and SRAMs (static RAMs) which is capable of supporting 5-V hot-carrier-hard circuit designs. In these designs the maximum drain-to-source voltage across a 0.5- mu m NMOS device is restricted to 4 V to ensure hot carrier reliability using 12-nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5-V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 ps/pF, which is 30% smaller than the load drive factor for the same basic design gate built using an 0.8- mu m process with 20-nm gate oxide. The authors also discuss how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5- mu m BiCMOS process. The addition of these components permits a 23- mu m/sup 2/ stacked 6-T CMOS SRAM cell to be realized, suitable for 4-Mb-class BiCMOS SRAMs.<<ETX>>

Performance of Submicron Silicon MOSFETs Fabricated by Edge-Defined Vertical-Etch Technique

This paper describes the performance of n-channel and p-channel submicrometer silicon MOS devices fabricated by edge-defined vertical etch techniques. Submicrometer MOS devices with gate length of 0.3 to 0.6 μm and gate oxide thickness of 8 to 16 nm have been fabricated with self-aligned, lightly doped source/drain extensions using a sidewall oxide spacer technology. Some of the devices have been fabricated with PtSi formed on the gate and source/drain to reduce series resistance. Mobility, linear and saturation gain, and drain saturation current have been examined as a function of gate length. Finally, ring oscillator performance for both n-channel and p-channel devices is discussed.