Horst L. Fiedler

A Memristor SPICE Implementation and a New Approach for Magnetic Flux-Controlled Memristor Modeling

This paper introduces a behavior model of a memristive soild-state device for simulation with a simulation program for integrated circuits emphasis (SPICE) compatible circuit simulator. After showing the underlying functional mechanics and model equations of a memristor the SPICE equivalent circuit based on a charge controlled memristor is presented and discussed. Hereafter, a magnetic flux controlled memristor model is introduced including technical description and SPICE implementation. It is shown that the presented SPICE models meet the requirements for simulations of multi memristor circuits.

An Advanced LOCOS-Process for the Sub-50 nm-Region Using Low-Stress PECVD-Silicon Nitrides

The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm [1]. When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.

Parameter Fluctuations in Multiple Patterned Deca-nm Scaled CMOS Structures

Multiple Patterning Seems to Be One of the Most Promising Solutions for the Gap between the 193 Nm Immersion Lithography and the 13.5 Nm EUV Lithography for Industrial Manufacturing of Ultra Large Scaled Integrated CMOS Circuits [1]. the Used Techniques in this Paper Lead to an Excellent Homogeneity and Uniformity of the Channel Length and Width which Enables a Fundamental Statistical Analysis of the Electrical Transistor Parameters. the Process Flow Has Been Optimized to Minimize the Active Channel Area and to Achieve a Sufficient Yield for a Trustworthy Statistical Analysis. while the Channel Length Is Defined by a Single Deposition- and Etchback Technique the Active Area Is Defined by a Composition of Multiple Spacers that Lead to a Diffusion Stop Barrier. the Statistical Analysis of these Devices Shows Dramatically Increasing Fluctuations of the Threshold Voltage if the Device Dimensions Are Decreased.

Creating a Monocrystalline Membrane via Etching and Sealing of Nanoholes Considering its Sealing Behavior

Based on silicon on insulator (SOI) technology [, a monocrystalline membrane is fabricated, in which a buried silicon dioxide layer in the silicon material is the sacrifice layer for the cavity. The membrane is a monocrystalline silicon top layer which contains nanoholes for creating the cavity in the buried oxide (BOX). To encapsulate the cavity the holes are sealed by using different techniques like non-stressed plasma-enhanced chemical vapour deposited (PECVD)-nitride and-oxide, thermal oxidation and evaporation of aluminum. To determine the sticking behavior of the membrane different sizes of membranes are fabricated and compared due to their sticking behavior. The experimental result shows that a membrane, having the size of 25 μm × 25 μm or below, has a perfect non-sticking behavior and can be used for further fabrication (cf. Fig. 8). For comparison, Figure 9 shows a membrane which delivers sticking behavior. The knowledge of this work can be widely used for several applications that need a cavity with a monocrystalline membrane like an absolute pressure sensor with a fully integrated CMOS-circuit on top of it [. This delivers a large variety of possibilities for novelty MEMS devices in different fields of research.

Wafer Extension for Cost-Effective Front to Back Side Alignment

This work presents a cost-effective and simple possibility to outperform the potential of a standard single side mask aligner. The limited functionality is extended to the capability of back side alignment with minimal effort without additional knowledge and integration of new process technologies. The whole presented process flow performs without the necessity of additional equipment as infrared back side wafer alignment kits or additional etching processes or clamps and brackets. The result is a front to back side alignment process with satisfactory deviation.

Spicedim - a CAD tool for supporting circuit sizing of analog CMOS circuits

This paper introduces Spicedim, a graphical programming interface for integrated CMOS circuit design. It connects the SPICE netlist level to an easy to use programming language, both combined in a graphical development environment. After classifying the context of this tool the fundamental application for parametric circuit simulation and signal processing is shown. This is done at the example of a parameterizable netlist for a current mirror. Further on, Spicedim supports calculations at single MOS-device for a device by device circuit sizing concept. Normally required input parameters for SPICE can be set to be calculated in dependence of specified normally calculated output parameters.

Cost-effective MOSFET-transistors on bulk silicon in the deep sub-50 nm-region

The potential of bulk silicon with classical gate oxides and poly silicon gate electrodes has not come to its end yet. This paper discusses the possibility to produce conventional MOS-Transistors on bulk silicon in the deep sub-50 nm-region with extreme low demands to the used substrate and process equipment. A process that uses a modified local oxidation of silicon technique with low and high frequency induced plasma enhanced vapour deposited nitrides as oxygen diffusion mask is introduced. It can be combined with a deposition and etchback technique. The essential process parameters of the LF/HF-nitride deposition are discussed. After the simulation of the necessary dopant profiles the results are compared to the experimental data.