Klaus T. Kallis

Visibility of two-dimensional layered materials on various substrates

For the investigation of 2D layered materials such as graphene, transition-metal dichalcogenides, boron nitride, and their heterostructures, dedicated substrates are required to enable unambiguous identification through optical microscopy. A systematic study is conducted, focusing on various 2D layered materials and substrates. The simulated colors are displayed and compared with microscopy images. Additionally, the issue of defining an appropriate index for measuring the degree of visibility is discussed. For a wide range of substrate stacks, layer thicknesses for optimum visibility are given along with the resulting sRGB colors. Further simulations of customized stacks can be conducted using our simulation tool, which is available for download and contains a database featuring a wide range of materials.

Optimizing the identification of mono- and bilayer graphene on multilayer substrates

This work presents an investigation and optimization of the identification of graphene mono- and bilayers on various multilayer substrates. Instead of the mere contrast between substrate and substrate/mono/bilayer systems, weighted color differences are used to obtain optimum visibility. Our approach employs a genetic algorithm that allows finding the most appropriate composition of multilayer systems in terms of materials in use and their respective thicknesses. A major benefit of our approach is the possibility to qualify appropriate layer systems with respect to their manufacturability.

Gate-Controlled WSe2 Transistors Using a Buried Triple-Gate Structure

In the present paper, we show tungsten diselenide (WSe2) devices that can be tuned to operate as n-type and p-type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake. Source, channel, and drain areas of the WSe2 flake are adjusted, using buried triple-gate substrates with three independently controllable gates. The device characteristics found in the tunnel transistor configuration are determined by the particular geometry of the buried triple-gate structure, consistent with a simple estimation of the expected off-state behavior.

Tackling hillocks growth after aluminum CMP

The surface of polished aluminum damascene structures is subject to strong growth of hillock structures, which is increased by elevated temperatures. Such hillock structures interfere with subsequent processing and should therefore be removed. We present an easy “repolishing” method, which employs provoked post-CMP growth of hillocks by annealing, and subsequent removal of the newly grown hillocks by a short, additional polishing step. Investigation with atomic-force and secondary electron microscopy indicates a significant decrease of the density and height of the hillock structures.

Backside Illumination of an Electronic Photo Ionization Detector Realized by UV Transparent Thin Films

LaB6/ITO films were prepared by magnetron sputtering technique on borosilicate glass substrates. The transmittance of ITO and LaB6/ITO films was analyzed by using UV/VIS spectrophotometer, whereby the sheet resistance of the ITO films was measured by four point probes. The effect of temperature and post-annealing processes on ITO film properties optimizing UV transparency and sheet resistance were investigated in detail. ITO films with an optimized thickness of 31 nm exhibited a low sheet resistance of 64 Ω/sq and a high ultraviolet transmittance of 81% at a wavelength of 365 nm. The additional LaB6 layer controls the UV transmittance behavior of the bilayer structure of LaB6/ITO by improving the photon absorption with thicker LaB6 films. The work function of LaB6 (32 nm)/ITO films with a value of 4.98 eV was measured by ultraviolet photoelectron spectroscopy (UPS).

An Advanced LOCOS-Process for the Sub-50 nm-Region Using Low-Stress PECVD-Silicon Nitrides

The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm [1]. When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.

Influence of Geometrical Factors on Performance of Thermoelectric Material Using Numerical Methods

Prediction of the performance of thermoelectric cooling material (figure of merit, ZT) was carried out by simulated results obtained from the finite element method (FEM) as a training dataset with an artificial neural network. A total of 87 input vectors for the ZT obtained from the four thermoelectric cooling (TEC) modules modeled using the FEM analysis were available in the training set to a back-propagation artificial neural network. An average correlation and maximum prediction error were found to be 100% and 0.01%, respectively, for the ZT after training. The standard deviation of the values was 0.05%. A set of test data, different from the training dataset was used to investigate the network performance. The average correlation and maximum prediction error were found to be 99.92% and 0.07%, respectively, for the tested TEC module. A thermoelectric module produced based on the numerical results was shown to be a promising device for use in cooling systems.

Performance of Novel Thermoelectric Cooling Module Depending on Geometrical Factors

A geometrical shape factor was investigated for optimum thermoelectric performance of a thermoelectric module using finite element analysis. The cooling power, electrical energy consumption, and coefficient of performance were analyzed using simulation with different current values passing through the thermoelectric elements for varying temperature differences between the two sides. A dramatic increase in cooling power density was obtained, since it was inversely proportional to the length of the thermoelectric legs. An artificial neural network model for each thermoelectric property was also developed using input–output relations. The models including the shape factor showed good predictive capability and agreement with simulation results. The correlation of the models was found to be 99%, and the overall prediction error was in the range of 1.5% and 1.0%, which is within acceptable limits. A thermoelectric module was produced based on the numerical results and was shown to be a promising device for use in cooling systems.

A monocrystalline absolute pressure sensor with a pseudo-MOSFET read-out device for life-science applications

Based on silicon on insulator (SOI) technology, a novel absolute pressure sensor with a pseudo-MOSFET read-out is designed and fabricated, in which a buried silicon dioxide layer in the silicon material is the sacrifice layer for the cavity. The membrane is a monocrystalline silicon top layer which contains nanoholes (120 nm × 2 μm) created by electron-beam lithography [1]. These nano-holes are used for isotropic etching of the cavity into the buried oxide (BOX). This idea based on the previous work of Lee et al. [2] and Sato et al. [3]. To encapsulate the cavity the holes are sealed by using non-stressed PECVD-nitride. The drain- and source-connections of the pseudo-MOSFET are compounded by evaporation of aluminum on top of the membrane and a backside metallization is attached for the gate connection. The experimental results show that this kind of sensor possesses good static performance, which meet the sophisticated pressure measurement demands of the medical industry.

Parameter Fluctuations in Multiple Patterned Deca-nm Scaled CMOS Structures

Multiple Patterning Seems to Be One of the Most Promising Solutions for the Gap between the 193 Nm Immersion Lithography and the 13.5 Nm EUV Lithography for Industrial Manufacturing of Ultra Large Scaled Integrated CMOS Circuits [1]. the Used Techniques in this Paper Lead to an Excellent Homogeneity and Uniformity of the Channel Length and Width which Enables a Fundamental Statistical Analysis of the Electrical Transistor Parameters. the Process Flow Has Been Optimized to Minimize the Active Channel Area and to Achieve a Sufficient Yield for a Trustworthy Statistical Analysis. while the Channel Length Is Defined by a Single Deposition- and Etchback Technique the Active Area Is Defined by a Composition of Multiple Spacers that Lead to a Diffusion Stop Barrier. the Statistical Analysis of these Devices Shows Dramatically Increasing Fluctuations of the Threshold Voltage if the Device Dimensions Are Decreased.