John T. Horstmann

Matching analysis of deposition defined 50-nm MOSFET's

NMOS- and PMOS-transistors with geometries down to 50 nm are fabricated by conventional optical lithography using a deposition- and etchback technique for masking the polysilicon layer. The significant process steps, especially the specific gate definition process and the doping of the source/drain-extensions, are explained. These transistors are then characterized and proceedings to increase their performance are suggested. The local and global matching of sub-100-nm transistors is analyzed by a large number of measurements and compared to typical literature values and simulations. The law of area (/spl sigma/V/sub T//spl prop/1//spl radic/(W/spl middot/L)) is confirmed for device dimensions from W/L=10 /spl mu/m/1 /spl mu/m down to W/L=1 /spl mu/m/50 nm. Based on this law of area, considerations to reduce the threshold voltage scattering for sub-100-nm transistors will be suggested.

Negative differential resistance in ultrashort bulk MOSFETs

In our contribution negative differential resistance and single electron switching events in the channel of bulk MOSFETs with channel lengths down to 30 nm are demonstrated. First, reproducible unexpected periodic transconductance oscillations in the I/sub D/xV/sub G/ characteristics of nMOSFETs are presented. The oscillations, present from sub-threshold up to strong inversion, are reproducible from sample to sample and with temperature cycling. No dependency of the oscillation period on gate oxide thickness or channel length could be observed and the period of the oscillations does not change in magnetic fields up to 15 T. Various electric transport models for small size MOS systems are analyzed. For several reasons, Coulomb blockade seems to be a rather plausible explanation for the observed effects. In the second part, another single electron switching phenomenon is studied. Namely, oxide traps are used as a probe into the local channel surface potential. Locking at the bias point dependence of the random telegraph signal (RTS) it is possible to estimate the trap location along the channel. It is shown that the behavior of the RTS does depend upon the properties of the trap and channel electrons, making RTS analysis a valuable tool to study effects as coulomb scattering, electron gas heating and the mechanisms that influence electrical channel formation in very small area devices.

Characterisation of sub-100 nm-MOS-transistors processed by optical lithography and a sidewall-etchback technique

This paper describes the fabrication of NMOS-transistors with a geometric gate length of down to 50 nm using conventional optical lithography and a modified sidewall-etchback process. Based on measurements the transistors are characterised and their device parameters are compared to simulations. Finally the procedures for further optimisation of the process will be explained.

1/f-Noise of sub-100 nm-MOS-transistors fabricated by a special deposition and etchback technique

The flicker noise (also called 1/f-noise) of NMOS-transistors with a channel length down to 80 nm is analyzed im comparison to the 1/f-noise of standard transistors with identical doping and gateoxide thickness by a large number of measurements. It is shown that the noise of sub-100 nm-MOS-transistors is increasing very strongly in comparison to standard transistors with a channel length in the micrometer region, but that the principal behavior of this noise phenomenon does not differ significantly from already known models.

Optimization of trench manufacturing for a new high-voltage semiconductor technology

Deep trenches for device insulation in a high-voltage process in thick SOI were fabricated using different manufacturing technologies. The trenches have been investigated by current-voltage-characteristics. In comparison to the conventional produced trenches alternatively fabricated samples reach a remarkable increase of the breakdown voltages accompanied by a decline of the leakage current in the order of several magnitudes. Respecting other process parameters a trench fabrication method has been selected which enables the manufacturing of reliable single trenches suitable for operating voltages up to 650 V. The new trench can be implied within a prospective X-FAB process. A reduction of area consumption is possible in many designs by replacing double trenches by single trenches. The future high-voltage X-FAB process will include new primitive devices which are currently designed and characterized. In this work new diode types with characteristic properties are presented.

Electrical characterization of different DEPFET designs on die level

For the future X-ray astronomy project Advanced Telescope for High ENergy Astrophysics plus (ATHENA+) wafer-scale DEpleted P-channel Field Effect Transistor (DEPFET) detectors are proposed as Focal Plane Array (FPA) for the Wide Field Imager (WFI). Prototype structures with different pixel layouts, each consisting of 64 x 64 pixels, were fabricated to study four different DEPFET designs. We report on the results of the electrical characterization of the different DEPFET designs. The transistor properties of the DEPFET structures are investigated in order to determine whether the design intentions are reflected in the transistor characteristics. In addition yield and homogeneity of the prototypes can be studied on die, wafer and batch level for further improvement of the production technology with regard to wafer-scale devices. These electrical characterization measurements prove to be a reliable tool to pre-select the best detector dies for further integration into full detector systems.

Parameter Fluctuations in Multiple Patterned Deca-nm Scaled CMOS Structures

Multiple Patterning Seems to Be One of the Most Promising Solutions for the Gap between the 193 Nm Immersion Lithography and the 13.5 Nm EUV Lithography for Industrial Manufacturing of Ultra Large Scaled Integrated CMOS Circuits [1]. the Used Techniques in this Paper Lead to an Excellent Homogeneity and Uniformity of the Channel Length and Width which Enables a Fundamental Statistical Analysis of the Electrical Transistor Parameters. the Process Flow Has Been Optimized to Minimize the Active Channel Area and to Achieve a Sufficient Yield for a Trustworthy Statistical Analysis. while the Channel Length Is Defined by a Single Deposition- and Etchback Technique the Active Area Is Defined by a Composition of Multiple Spacers that Lead to a Diffusion Stop Barrier. the Statistical Analysis of these Devices Shows Dramatically Increasing Fluctuations of the Threshold Voltage if the Device Dimensions Are Decreased.

Single trench isolation for a 650 V SOI technology with low mechanical stress

The successful optimization and characterization of a deep trench isolation in a thick SOI process for operating voltages up to 650 V is reported. Different technologies were investigated to optimize the mechanical stress during wafer processing and to increase the breakdown voltage of a single trench configuration. Comprehensive electrical characterization was done to investigate achievable operating conditions and related reliability issues for thick oxide trench isolation layers. The most promising trench technology was choosen as a modular extension to an existing 650 V SOI BCD process.

Matching analysis of NMOS-transistors with a channel length down to 30 nm

NMOS-transistors with a gate length down to 30 nm are fabricated applying a modified deposition- and etchback-technique for gate definition using only conventional optical lithography. This leads to an excellent homogeneity and uniformity of the channel length which enables a trustworthy statistical analysis of the transistors. The influence of the inevitable statistical fluctuations of the channel doping on the fluctuations of the electrical device characteristics is examined. This local and global matching of the transistors with dimensions varying from W/L=10 /spl mu/m/1 /spl mu/m down to W/L=1 /spl mu/m/30 nm is analyzed by a large number of measurements. The results are compared to the law of area (/spl sigma/V/sub T//spl prop/1//spl radic/(W/spl middot/L)) showing a good agreement even for the smallest geometries.

Erweiterung konventioneller Bauelemente durch Nanotechniken

Die Reduktion der Dimensionen in elektronischen Bauelementen fuhrt einerseits zu leistungsfahigeren Transistoren, bewirkt andererseits aber auch statistische Fluktuationen in den Transistorparametern wie der Schwellenspannung oder der Steilheit. Zusatzlich treten bei tiefen Temperaturen neue Effekte auf, die noch nicht vollstandig erklart werden konnen. Die Auswirkung der Nanoskalierung auf Transistoren wird anhand gemessener Transistorparameter und Kennlinien diskutiert.