Hossein Kassiri

Low-distortion super-GOhm subthreshold-MOS resistors for CMOS neural amplifiers

A low-distortion super-GOhm subthreshold MOS resistor is designed, fabricated and experimentally validated. The circuit is utilized as a feedback element in the body of a two-stage neural recording amplifier. Linearity is experimentally validated for 0.5 Hz to 5 kHz input frequency and over 0.3 to 0.9 V output voltage dynamic range. The implemented pseudo resistor is also tunable, making the high-pass filter pole adjustable. The circuit is fabricated in 0.13-μm CMOS process and consumes 96 nW from a 1.2 V supply to realize an over 500 GΩ resistance.

Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio

An inductively powered 0.13μm CMOS neurostimulator SoC for intractable epilepsy treatment is presented. Digital offset cancellation yields a compact 0.018mm2 DC-coupled neural recording front-end. Input chopper stabilization is performed on all 64 channels resulting in a 4.2μVrms input-referred noise. A tri-band FSK/UWB radio provides a versatile transcutaneous interface. The inductive powering system includes a 20mm × 20mm 8-layer flexible receiver coil with 40% power transfer efficiency. In-vivo chronic epilepsy treatment experimental results show an average sensitivity and specificity of seizure detection of 87% and 95%, respectively, with over 76% of all seizures aborted.

Battery-less Tri-band-Radio Neuro-monitor and Responsive Neurostimulator for Diagnostics and Treatment of Neurological Disorders

A 0.13 μm CMOS system on a chip (SoC) for 64 channel neuroelectrical monitoring and responsive neurostimulation is presented. The direct-coupled chopper-stabilized neural recording front end rejects up to ±50 mV input dc offset using an in-channel digitally assisted feedback loop. It yields a compact 0.018 mm2 integration area and 4.2 μVrms integrated input-referred noise over 1 Hz to 1 kHz frequency range. A multiplying specific absorption rate (SAR) ADC in each channel calibrates channel-to-channel gain mismatch. A multicore low-power DSP performs synchrony-based neurological event detection and triggers a subset of 64 programmable current-mode stimulators for subsequent neuromodulation. Triple-band FSK/ultra-wideband (UWB) wireless transmitters communicate to receivers located at 10 cm to 10 m distance from the SoC with data rates from 1.2 to 45 Mbps. An inductive link that operates at 1.5 MHz, provides power and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 16 mm2 while consuming 2.17 and 5.8 mW with UWB and FSK transmitters, respectively. Efficacy of the SoC is assessed using a rat model of temporal lobe epilepsy characterized by spontaneous seizures. It exhibits an average seizure detection sensitivity and specificity of 87% and 95%, respectively, with over 78% of all seizures aborted.

Rapid brief feedback intracerebral stimulation based on real-time desynchronization detection preceding seizures stops the generation of convulsive paroxysms

To investigate the abortion of seizure generation using “minimal” intervention in hippocampi using two rat models of human temporal lobe epilepsy.

Battery-less modular responsive neurostimulator for prediction and abortion of epileptic seizures

An inductively-powered implantable microsystem for monitoring and treatment of intractable epilepsy is presented. The miniaturized system is comprised of two mini-boards and a power receiver coil. The first board hosts a 24-channel neurostimulator SoC developed in a 0.13μm CMOS technology and performs neural recording, electrical stimulation and on-chip digit l signal processing. The second board communicates recorded brain signals as well as signal processing results wirelessly, and generates different supply and bias voltages for the neurostimulator SoC and other external components. The multi-layer flexible coil receives inductively-transmitted power and sends it to the second board for power management. The system is sized at 2 × 2 × 0.7 cm3, weighs 6 grams, and is validated in control of chronic seizures in vivo in freely-moving rats.

27.3 All-wireless 64-channel 0.013mm 2 /ch closed-loop neurostimulator with rail-to-rail DC offset removal

Accurate capture and efficient control of neurological disorders such as epileptic seizures that often originate in multiple regions of the brain, requires neural interface microsystems with an ever-increasing need for higher channel counts. Addressing this demand within the limited energy and area of brain-implantable medical devices necessitates a search for new circuit architectures. In the conventional designs [1–5], the channel area is dominated by the bulky coupling capacitors and/or capacitor banks of the in-channel ADC, both unavoidable due to the channel architecture, and unscalable with CMOS technology. Additionally, channel power consumption, typically dominated by the LNA, cannot be reduced lower than a certain limit without sacrificing gain and/or noise performance. In this paper, we present a 64-channel wireless closed-loop neurostimulator with a compact and energy-efficient channel architecture that performs both amplification and digitization in a single ΔΣ-based neural ADC, while removing rail-to-rail input DC offset using a digital feedback loop. The channel area and power consumption depend only on the active components and switching frequency, respectively, making the design both technology- and frequency-scalable.

Wearable low-latency sleep stage classifier

A wearable microsystem for low-latency automatic sleep stage classification and REM sleep detection in rodents is presented. The detection algorithm is implemented digitally to achieve low latency and is optimized for low complexity and power consumption. The algorithm uses both EEG and EMG signals as inputs. Experimental results using off-line signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.83%, respectively, with a latency of 39μs. The system will be used in a non-disruptive closed loop REM sleep suppression microsystem to study the effects of REM sleep deprivation on memory consolidation.

Electronic Sleep Stage Classifiers: A Survey and VLSI Design Methodology.

First, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low-latency automatic sleep stage classification in rodents is presented. The classification algorithm uses one EMG (electromyogram) and two EEG (electroencephalogram) signals as inputs in order to detect REM (rapid eye movement) sleep, and is optimized for low complexity and low power consumption. It is implemented in an on-board low-power FPGA connected to a multi-channel neural recording IC, to achieve low-latency (order of 1 ms or less) classification. Off-line experimental results using pre-recorded signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.86%, respectively, with the maximum latency of 39

Inductively powered arbitrary-waveform adaptive-supply electro-optical neurostimulator

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Tradeoffs between wireless communication and computation in closed-loop implantable devices

. The device is designed to be used in a non-disruptive closed-loop REM sleep suppression microsystem, for future studies of the effects of REM sleep deprivation on memory consolidation.