Roman Genov

The 128-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interface

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg2+/high-K+ epileptic seizure model in an intact hippocampus of a mouse.

256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes

A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 times 16-channel neural recording interface integrated prototype fabricated in 0.35 mum CMOS occupies 3.5 mm times 4.5 mm area. Each recording channel dissipates 15 muW of power with input-referred noise of 7 muVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology.

Kerneltron: support vector "machine" in silicon

Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment; and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 mm/spl times/3mm in 0.5 /spl mu/m CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.

16-Channel Integrated Potentiostat for Distributed Neurochemical Sensing

We present the architecture and VLSI circuit implementation of a BiCMOS potentiostat bank for monitoring neurotransmitter concentration on a screen-printed carbon electrode array. The potentiostat performs simultaneous acquisition of bidirectional reduction-oxidation currents proportional to neurotransmitter concentration on 16 independent channels at controlled redox potentials. Programmable current gain control yields over 100-dB cross-scale dynamic range with 46-pA input-referred rms noise over 12-kHz bandwidth. The cutoff frequency of a second-order log-domain anti-aliasing filter ranges from 50 Hz to 400 kHz. Track-and-hold current integration is triggered at the sampling rate between dc and 200 kHz. A 2.25-mmtimes2.25-mm prototype was fabricated in a 1.2-mum VLSI technology and dissipates 12.5 mW. Chronoamperometry dopamine concentration measurements results are given. Other types of neurotransmitters can be selected by adjusting the redox potential on the electrodes and the surface properties of the sensor coating

Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor

The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8 pixels in parallel directly on the focal plane. Three operations, a temporal difference, a multiplication and an accumulation are performed for each pixel readout. A dual-memory pixel stores two video frames. Selective pixel output sampling controlled by binary kernel coefficients implements binary-analog multiplication. Cross-pixel column-parallel bit-level accumulation and frame differencing are implemented by switched-capacitor integrators. Binary-weighted summation and concurrent quantization is performed by a bank of column-parallel multiplying analog-to-digital converters (MADCs). A simple digital adder performs row-wise accumulation during ADC readout. A 128 times 128 active pixel array integrated with a bank of 128 MADCs was fabricated in a 0.35 mum standard CMOS technology. The 4.4 mm times 2.9 mm prototype is experimentally validated in discrete wavelet transform (DWT) video compression and frame differencing.

Brain–Silicon Interface for High-Resolution in vitro Neural Recording

A 256-channel integrated interface for simultaneous recording of distributed neural activity from acute brain slices is presented. An array of 16 times 16 Au recording electrodes are fabricated directly on the die. Each channel implements differential voltage acquisition, amplification and band-pass filtering. In-channel analog memory stores an electronic image of neural activity. A 3 mm times 4.5 mm integrated prototype fabricated in a 0.35-mum CMOS technology is experimentally validated in single-channel extracellular in vitro recordings from the hippocampus of mice and in multichannel simultaneous recordings in a controlled environment

64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator

An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line.

A CMOS/Thin-Film Fluorescence Contact Imaging Microsystem for DNA Analysis

A hybrid CMOS/thin-film microsystem for fluorescence contact imaging is presented. The microsystem integrates a high-performance optical interference filter and a 128 × 128 pixel active pixel sensor fabricated in a standard 0.35-¿m CMOS technology. The thin-film filter has an optical density greater than 6.0 at the wavelength of interest, providing adequate excitation rejection to the 532-nm solid-state laser. Microsystem performance is experimentally validated by imaging spots of Cyanine-3 fluorophore, conventionally used in DNA detection. The emission intensity as a function of fluorophore concentration is measured with an estimated sensitivity of 5000 fluorophore/¿m2 . A human DNA microarray has been imaged with the sensor prototype.

320-Channel Active Probe for High-Resolution Neuromonitoring and Responsive Neurostimulation

We present a 320-channel active probe for high-spatial-resolution neuromonitoring and responsive neurostimulation. The probe comprises an integrated circuit (IC) cell array bonded to the back side of a pitch-matched microelectrode array. The IC enables up to 256-site neural recording and 64-site neural stimulation at the spatial resolution of 400 μm and 200 μm, respectively. It is suitable for direct integration with electrode arrays with the shank pitch of integer multiples of 200 μm. In the presented configuration, the IC is bonded with a 8 × 8 400 μm-pitch Utah electrode array (UEA) and up to additional 192 recording channels are used for peripheral neuromonitoring. The 0.35 μm CMOS circuit array has a total die size of 3.5 mm × 3.65 mm. Each stimulator channel employs a current memory for simultaneous multi-site neurostimulation, outputs 20 μA-250 μA square or arbitrary waveform current, occupies 0.02 mm 2, and dissipates 2.76 μW quiescent power. Each fully differential recording channel has two stages of amplification and filtering and an 8-bit single-slope ADC, occupies 0.035 mm 2 , and consumes 51.9 μW. The neural probe has been experimentally validated in epileptic seizure propagation studies in a mouse hippocampal slice in vitro and in responsive neurostimulation for seizure suppression in an acute epilepsy rat model in vivo .

CMOS Neurotransmitter Microarray: 96-Channel Integrated Potentiostat With On-Die Microsensors

A 8 × 12 array of integrated potentiostats for on-CMOS neurotransmitter imaging is presented. Each potentiostat channel measures bidirectional redox currents proportional to the concentration of a neurochemical. By combining the current-to-frequency and the single-slope analog-to-digital converter (ADC) architectures a total linear dynamic range of 95 dB is achieved. A 3.8 mm × 3.1 mm prototype fabricated in a 0.35 μm standard CMOS technology was integrated with flat and 3D on-die gold microelectrodes and an on-chip microfluidic network. It is experimentally validated in in-situ recording of neurotransmitter dopamine.