Torsten Lehmann

1-V power supply CMOS cascode amplifier

We design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69-dB DC gain, a 2-MHz bandwidth, and compatible input- and output voltage levels at a 1-V power supply. This is done by a novel, current driven bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

Integrating data converters for picoampere currents from electrochemical transducers

This paper describes a current mode A/D converter designed for a maximum input current range of 5 nA and a resolution of the order of 1 pA. The converter is designed for a potentiostat for amperometric chemical sensors and provides a constant polarization voltage for the measuring electrode. A prototype chip using the dual slope conversion method has been fabricated in a 0.7 /spl mu/m CMOS process. Experimental results from this converter are reported. Design problems and limitations of the converter are discussed and a new conversion technique providing a larger dynamic range and easy calibration is proposed.

An Implantable CMOS Amplifier for Nerve Signals

AbstractIn this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/

1 V OTA USING CURRENT DRIVEN BULK CIRCUITS

\sqrt {{\text{Hz}}}

An implantable CMOS amplifier for nerve signals

. The amplifier power consumption is 275 μW, drawn from a power supply; VDD = −VSS = 1.5 V.

Low Power CMOS Interface Circuitry for Sensors and Actuators

Self-learning chips to implement many popular ANN (artificial neural network) algorithms are very difficult to design. We explain why this is so and say what lessons previous work teaches us in the design of self-learning systems. We offer a contribution to the “biologically-inspired” approach, explaining what we mean by this term and providing an example of a robust, self-learning design that can solve simple classical-conditioning tasks. We give details of the design of individual circuits to perform component functions, which can then be combined into a network to solve the task. We argue that useful conclusions as to the future of on-chip learning can be drawn from this work.

Ultra-low voltage CMOS cascode amplifier

We show how the MOST threshold voltage can be reduced simply by forcing a constant current through the transistor bulk terminal. We characterize two versions of the resulting current driven bulk device by simulations, and conclude that this is a good method for improving circuit performance when the voltage supply is very low. Finally we show how the technique can be used to implement a 1 V folded cascode OTA with compatible input and output voltage ranges.

Current-Mode CMOS A/D Converter for pA to nA Input Currents

A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANNs):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution.