Kuang-Hao Lin

Iterative

Implementation of an iterative QR decomposition (QRD) (IQRD) architecture based on the modified Gram-Schmidt (MGS) algorithm is proposed in this paper. A QRD is extensively adopted by the detection of multiple-input-multiple-output systems. In order to achieve computational efficiency with robust numerical stability, a triangular systolic array (TSA) for QRD of large-size matrices is presented. In addition, the TSA architecture can be modified into an iterative architecture that is called IQRD for reducing hardware cost. The IQRD hardware is constructed by the diagonal and the triangular process with fewer gate counts and lower power consumption than TSAQRD. For a 4 t 4 matrix, the hardware area of the proposed IQRD can reduce about 41% of the gate counts in TSAQRD. For a generic square matrix of order m IQRD, the latency required is 2m - 1 time units, which is based on the MGS algorithm. Thus, the total clock latency is only 10 m - 5 cycles.

QR

Implementation of an iterative QR decomposition (QRD) (IQRD) architecture based on the modified Gram-Schmidt (MGS) algorithm is proposed in this paper. A QRD is extensively adopted by the detection of multiple-input-multiple-output systems. In order to achieve computational efficiency with robust numerical stability, a triangular systolic array (TSA) for QRD of large-size matrices is presented. In addition, the TSA architecture can be modified into an iterative architecture that is called IQRD for reducing hardware cost. The IQRD hardware is constructed by the diagonal and the triangular process with fewer gate counts and lower power consumption than TSAQRD. For a 4 × 4 matrix, the hardware area of the proposed IQRD can reduce about 41% of the gate counts in TSAQRD. For a generic square matrix of order m IQRD, the latency required is 2m - 1 time units, which is based on the MGS algorithm. Thus, the total clock latency is only 10 m - 5 cycles.

Decomposition Architecture Using the Modified Gram–Schmidt Algorithm for MIMO Systems

This study presents a high-precision real-time detection system to detect arrhythmia of premature ventricular contraction (PVC). This system detects the peak of the R-wave based on wavelet transform (WT) and then uses a new algorithm to detect PVC. The proposed PVC detection algorithm combines the sum of trough and sum of R_peak with minimum to detect PVC. A crucial function of morbid warning is implemented in this system so that users receive an alert signal when PVC is detected. The proposed system is simulated and verified using the MIT-BIH Arrhythmia Database (mitdb). The system is also implemented by FPGA to illustrate its high precision and real-time performance.

Iterative QR decomposition architecture using the modified Gram-Schmidt algorithm

In modern Wireless Local Area Network (WLAN), both the transmitting data throughput and the connecting stability are very important. For the IEEE802.11n protocol specification, it is made of a multi-input multi-output (MIMO) system and an Orthogonal Frequency Division Multiplexing (OFDM) system. In order to decrease the decoding error rate at the receiving end and to fully restore the original transmitting signal, estimation of the channel response information is necessary. In this paper, a combined channel estimation algorithm is proposed by using TDT-L-STBC, which can increase the MIMO channel estimation performance. The proposed architecture of MIMO-2×2 is implemented and verified by TSMC 0.18 μm CMOS technology.

High-Precision Real-Time Premature Ventricular Contraction (PVC) Detection System Based on Wavelet Transform

This paper presents a low power CMOS RF front-end with a low noise amplifier (LNA) and mixer for long term evolution (LTE) direct conversion receiver. Noise figure and linearity are key parameter of LTE receiver front-end. The source inductive degeneration LNA is designed achieving matched input impedance over a wide bandwidth. For low power consumption issue, a direct conversion receiver with LNA and mixer employ folded-cascode architecture. The receiver front-end operates from 2545 to 2700 MHz covering frequency band 7 of LTE standard. The front-end achieves 8.89 dB conversion gain, 8.25 dB NF, -9.5 dBm IIP3, -17 dBm P1dB and 3.12 mW power consumption. All the circuits are designed in 0.18 μm CMOS process with 1.2V supply voltage.

Implementation of channel estimation for MIMO-OFDM systems

This paper presents a low-power, variable block-size and irregular LDPC decoding. Our proposed LDPC decoder uses nanometer technology running the well-known TDMP and SMSA decoding algorithm. We further improved the design with pipeline structure, parallel computation and without any memory unit. Therefore, we can utilize only one routing network to route three different block-size data. The prototype architecture is being implemented on 90 nm VLSI technology. Because this VLSI technology has multi-Vth layers, we can make the design more effective. Compared to recent state-of-the-art architectures, the proposed variable block-size LDPC decoder has 450 MHz clock frequency, 349.48 K gate counts, 168 mW power dissipation, and 1.215 Gbps throughput.

A low power CMOS receiver front-end for long term evolution systems

This paper presents a high-efficiency monolithic dc-dc PFM boost converter designed with a standard TSMC3.3/5V 0.35 µm CMOS technology. The proposed boost converter combines the parallel power MOS technique with pulse-frequency modulation (PFM) technique to achieve high efficiency over a wide load current range, extending battery life and reducing the cost for the portable systems. The proposed parallel power MOS controller and load current detector exactly determine the size of power MOS to increase power conversion efficiency in different loads. Postlayout simulation results of the designed circuit show that the power conversion is 74.9-90.7% efficiency over a load range from 1mA to 420mA with 1.5V supply. Moreover, the proposed boost converter has a smaller area and lower cost than those of the existing boost converter circuits.

Low-power design of variable block-size LDPC decoder using nanometer technology

This paper presents a modified implementation of QR decomposition for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) detection based on the Givens rotation method. The QR decomposition hardware is constructed using the coordinate rotation digital computer (CORDIC) algorithm operating with fewer gate counts and lower power consumption than do triangular systolic array (TSA) structures. Accurate signal transmission is essential to wireless communication systems. Thus, a more effective data detection algorithm and precise channel estimation method play vital roles in MIMO systems. Implementing data detection with QR decomposition helps reduce the complexity of MIMO-OFDM detection. Implementation results reveal that the proposed recursive QR decomposition (RQRD) architecture has lower clock latency than do TSA structures, and has a smaller hardware area than do Gram–Schmidt structures.

A high-efficiency monolithic DC-DC PFM boost converter with parallel power MOS technique

This study presents a multimedia game development system that integrates an intelligent mobile with an embedded platform. Based on the excellent multi-functional sensing components of intelligent mobile phones (including gravity sensors and touch panels) and Bluetooth technology, the proposed communication protocol can control the proposed embedded platform system to ensure that all the platform abilities can allow the system to achieve a high level of applicability and amusement. Integrating intelligent mobile phones with the gaming industry can lead to the production of new forms of multimedia games, increasing the amusement of users.

RECURSIVE QR DECOMPOSITION ARCHITECTURE FOR MIMO-OFDM DETECTION SYSTEMS

The maximum likelihood (ML) detection is the optimal detection method for multiple-input multiple-output (MIMO) communication systems. The normal K-best Sphere Decoding Algorithm (SDA) can guarantee a fixed throughput, but it induces a large bit error rate (BER) degradation. In order to achieve close-to-ML performance, the K value needs to be sufficiently large. Thus, it needs large computation with long latency and low throughput. In this paper, a reconfigurable K-best SDA is proposed by using fixed K values for different layers of K-best detection, which can increase the MIMO detection performance. The architecture of 4×4 MIMO detector is designed for both 16QAM and 64QAM modulation.