Hridoy Jyoti Mahanta

Networks on Chip: The New Trend of On-Chip Interconnection

With continuous shrinking in the size of deep sub-micron in this million transistor era, the interconnection of these hundreds and thousands of cores on a single chip is still constraint. Providing an efficient communication among these cores is a major challenge in the on-chip domain. Although hierarchical architecture has addressed most of the issues of the traditional approaches like point-to-point and bus architecture, scalability still remains to be a limitation. Network on chip architecture provides a viable solution to all these issues. A network is established on the chip among the cores and communication occurs through this network, making it highly efficient and mostly scalable. In this paper we present a brief introduction to network-on-chip along with some of its popular topologies and routing techniques. Also, some of the major challenges of network-on-chip have been stated.

Implementing a partial group based routing for homogeneous fat tree network on chip architecture

As the growing consumer electronic market imposes constraint such as compact product design and strict time to market, the traditional method of chip designing failed miserably to satisfy these constraints. With the evolution of Network-on-Chip, researchers have made an honest effort to resolve such issues but designing a network which encourages reusability of components and also scalable still remains an area where more refinement is necessary. In this paper we present before you a fat tree based network on chip. The entire design of the network with the nodes and switches has been described in details. The proposed architecture has been implemented and analyzed in a C++ based simulator. The analysis results have been presented at the end of the paper.

Differential Power Analysis: Attacks and Resisting Techniques

Differential Power Analysis (DPA) is a statistical approach to analyze the power consumption of a cryptographic system to break its security infrastructure. It has challenged the vulnerability of most of the cryptographic techniques like DES, AES, RSA etc. With DPA, attackers passively collect the power traces of the system and then make a comparative analysis with some hypothetical power traces. The analysis result having high value reveals the secret key used. This kind of attack has been explored by many researchers and has proposed techniques to make such attacks highly efficient. In this paper we present a detail on DPA along with the models and types for such attack. We also present some of the recent attack techniques as well as countermeasures on DPA.

Power analysis attack: A vulnerability to smart card security

A major breakthrough in side channel attacks came up when analysis of power consumption by a cryptographic device led to discovery of the secret key. This analysis technique popularly known as Power Analysis Attack is now one of the most volatile and successful side channel attacks. This technique uses the power consumed by a cryptographic system as the main parameter to identify the cryptographic algorithms as well as the secret key used. The power traces of the system are statistically analyzed and the correlation between these traces and the cryptographic technique is explored to break the security. This attack has been successfully carried out on various cryptographic algorithms like DES, AES, RSA and ECC which are implemented on cryptographic devices such smart cards, FPGA, DSP, ASIC etc. In this paper we present a review on the power analysis attack and its techniques. Also, a brief detail on some of the power analysis attacks on smart card and FPGA have been presented. Couple of methods to improve such attacks has also been mentioned.

Side channel attacks and their mitigation techniques

Side channel cryptanalysis is one of the most volatile fields of research in security prospects. It has proved that cryptanalysis is no more confined to its dependence on plain text or cipher text. Indeed side channel attack uses the physical characteristics of the cryptographic device to find the cryptographic algorithm used and also the secret key. It is one of the most efficient techniques and has successfully broken almost all the cryptographic algorithms today. In this paper we aim to present a review on the various side channel attacks possible. Also, the techniques proposed to mitigate such an attack have been stated.

Improving Power Analysis Peak Distribution Using Canberra Distance to Address Ghost Peak Problem

This article describes how differential power analysis has laid the foundations of such an attack that has challenged the security of almost all cryptosystems like DES, AES, and RSA. This non-invasive attack first extracts the power consumption details from devices embedded with cryptographic techniques and then uses these details to mount attacks on the cryptosystems to reveal the secret key. However, at times there appears multiple similar power peaks at the same points. This raises confusion in distinguishing the actual and the fake peaks named “ghost peaks.” This ghost peak problem affects the efficiency of power analysis attacks as it increases the number of power traces to be evaluated to identify the actual peak. In this article, the authors present an approach which uses the Canberra distance with Euclidean similarity to address this ghost peak problem. The proposed solution diminishes the values of all these ghost peaks, leaving only the actual peak behind that could reveal the secret key.

A randomization based computation of RSA to resist power analysis attacks

This paper presents an overview on the randomization technique. Randomization has been considered as one of the efficient techniques to resist power analysis attack on exponentiation based cryptographic algorithm. RSA is one of the most widely used public key cryptosystem. It uses exponentiation operation for encryption / decryption of data. If the instantaneous power consumed during the exponential operation is monitored, it could reveal the operation as well as secret data. Here we have proposed a randomization based exponentiation calculation method that could resist power analysis attacks on RSA.

Securing RSA against power analysis attacks through non-uniform exponent partitioning with randomisation

This study presents an approach to compute randomised modular exponentiation through non-uniform exponent partitioning. The exponent has been first partitioned into multiple parts and then shuffled by Fisher Yates method. Thereafter, every partition randomly computes modular exponentiation followed by a final modulo operation to generate the desired result. The shuffling has been introduced to randomise the execution order of individual modular exponentiation. This work is implemented in Rivest-Shamir-Adleman (RSA) and Chinese remainder theorem RSA as they are modular exponentiation based public key cryptosystems. The results have been analysed during decryption with different key sizes. The results indicate that the proposed work can generate non-uniform partitions of the exponent which could not be easily anticipated even in multiple iterations. Also, the shuffling method could completely randomise the execution order of modular exponentiation operations. With non-uniform exponent partitions and randomised modular exponentiation, the proposed work could challenge all the variances of power analysis attacks.

A masking based RSA to resist power analysis attacks

In this paper we have presented a detail on masking which is a technique used to resist power analysis attacks. Some of the works that have been done using this technique have been analyzed. Also, a masking based approach for RSA has been proposed. The proposed works first masks the plaintext and then execute the RSA instructions. In between, some real time random instructions were also inserted which not only masked the values but also could provide variations in the power consumptions thus resisting power analysis attacks.

An architecture based routing for heterogeneous fat tree network on chip

With the evolution of network on chip, a number of topologies depicting the structure of the network came up. Classical network designs like star, mesh, ring were initially used but ongoing to its wide range of applications in real life network on a chip was much applicable in real time so factors like area, latency, placements of IPs were to be addressed. As a result, many new topologies like torus, spin, butterfly evolved which could address these issues. One of such topology which has been widely used is the fat tree. Unlike the conventional tree used in computation, the fat tree was more like a real tree making it highly efficient for supercomputing. Although, the architecture and routing in this network is predesigned, but it has been implemented in different environments and with different techniques. Here, we have designed an architecture based routing for the fat tree network with heterogeneous switches. Based on the results presented, it is seen that the new approach is performing much efficiently.