Md. Anwar Hussain

Networks on Chip: The New Trend of On-Chip Interconnection

With continuous shrinking in the size of deep sub-micron in this million transistor era, the interconnection of these hundreds and thousands of cores on a single chip is still constraint. Providing an efficient communication among these cores is a major challenge in the on-chip domain. Although hierarchical architecture has addressed most of the issues of the traditional approaches like point-to-point and bus architecture, scalability still remains to be a limitation. Network on chip architecture provides a viable solution to all these issues. A network is established on the chip among the cores and communication occurs through this network, making it highly efficient and mostly scalable. In this paper we present a brief introduction to network-on-chip along with some of its popular topologies and routing techniques. Also, some of the major challenges of network-on-chip have been stated.

Implementing a partial group based routing for homogeneous fat tree network on chip architecture

As the growing consumer electronic market imposes constraint such as compact product design and strict time to market, the traditional method of chip designing failed miserably to satisfy these constraints. With the evolution of Network-on-Chip, researchers have made an honest effort to resolve such issues but designing a network which encourages reusability of components and also scalable still remains an area where more refinement is necessary. In this paper we present before you a fat tree based network on chip. The entire design of the network with the nodes and switches has been described in details. The proposed architecture has been implemented and analyzed in a C++ based simulator. The analysis results have been presented at the end of the paper.

Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison

The paper presents a low power high speed Arithmetic Logic Unit (ALU) in 45 nm technology using Gate Diffusion Input (GDI) technique and its performance comparison with CMOS and nMOS Pass Transistor Logic (PTL) techniques. The simulated results revealed better performance characteristics of various logic and arithematic functions of a 1-bit ALU using GDI techniqueas compared to conventional CMOS and nMOS PTL techniques. GDI technique allows reducing power dissipation and delay while maintaining low complexity of logic design. MICROWIND and DSCH 3.1 EDA tools were used for the schematic layout and simulation of ALU using BSIM4 model.

Improving the performance of key pre-distribution scheme in sensor network using clustering of combinatorics

Key Pre-distribution Scheme in Wireless Sensor Network plays an important role of providing security to the network. A perfect key pre-distribution scheme provides better resiliency against malfunction of the sensor node or physical capture of nodes. Combinatorial design technique is well established method for KPS as it give excellent connectivity to the network. Also it is observed that good connectivity does not imply perfect resilience against node compromise. Resilience is the measure of ability of survival of the network in hostile environment. We propose a novel KPS based on combinatorial design, where nodes were clustered with the help of concept of formation of balanced incomplete blocks of combinatorial design theory. We have performed various experiments for performance analysis of the new proposed scheme showing the connectivity comparison, average hop count comparison and resilience measure with existing traditional KPS in various network scenarios.

A simple joint routing and scheduling algorithm for a multi-hop wireless network

Routing and scheduling in wireless multi-hop networks is challenging, particularly when there are large number of nodes. Simple route construction algorithm becomes attractive as it requires fewer computations. In this paper, a novel routing and scheduling algorithm is proposed, which can be implemented in centralized or distributed way. In this algorithm when the user node (U) tries to reach the base station (BS) through intermediate nodes (IMs), it draws a reference line to the BS, chooses the intermediate node at minimum angle with the reference line, from its neighboring nodes within one transmission range. The other links of the route to the BS through the IMs are also found in the same way. We call it minimum angle (MA) routing and distributed scheduling (DS), MA-DS. The minimum angle (MA) routing and centralized scheduling (CS) is initiated by the BS using the same principle to reach the user node (U), we call it MA-CS. The algorithm requires only the position (x-y co-ordinate) information and the burst profile of the nodes.

Eigenspace based accurate iris recognition system

Biometric object based person identification is now gaining reliability and high acceptability. Iris as biometric object is used for such identification in many important applications. Almost all techniques, that use iris for recognition is not fully accurate. In this paper we present an accurate iris recognition system that is based on feature extraction in the eigen space and treating the iris in the lower dimensionality. Eigen irises are constructed from a set of iris images of a person, and a given iris image is recognized by passing it through different sets of eigen irises obtained from the sets of iris images of different persons in the database. We considered different numbers of eigenirises for each person, and compressed and compressed noisy iris images as well as only noisy iris images for recognition. Results show accurate person identification using this technique.

Performance Analysis of Expander Graph Based Key Predistribution Scheme in WSN

Secret communication in Wireless Sensor Network is considered to be a challenging task due to high risk of node capture. Secret communication is only possible when communicating nodes share a common key for cryptographic purpose. Sensor nodes are often loaded with required secret key in its memory prior to deployment called key pre-distribution scheme (KPS). Various KPS have been proposed to provide secure communication and to minimize damage caused by intruder. In this paper, we will discuss properties of expander graph that are suitable in designing KPS and perform various experiments on KPS based on Ramanujan Expander graph for performance evaluation.

Secure energy aware multi-path routing with key management in wireless sensor network

With the ability to work under critical environments where human interception is difficult, wireless sensor networks serves as a useful communication means for data transmission and collection. But like other wireless networks WSN is also prone to adversary interventions. So the researchers are addressing this issue to make routing protocols secure for communication. But due to the severe resource constraints on sensor nodes like limited battery life and limited storage capacity prevents the traditional complex security mechanisms to be employed on the sensor nodes. In this paper we propose a new routing algorithm called Secure Energy Aware Multipath Routing with Key Management (SEAM-KM) in Wireless Sensor Network. This protocol focuses on using a base station as the central control block for all kinds of computation like shortest path selection, routing table generation, Updating the routing table and distribution of pair wise keys among the sensor nodes and the base station. Leaving the energy consuming computations to be performed by the base station, the lifetime of the sensor nodes can be prolonged. Moreover distribution of pair wise keys among sensor nodes provides security among sensor nodes and also increases the resilience of the network. This protocol is resistive to some of the specific attacks which rely on forming attractive routes to lure the sensor nodes to communicate through the already compromised nodes.

A multipath Network-on-Chip topology

Network-on-Chip (NoC) is a new on chip communication design system that replaced bus-based communication in System-on-Chip (SoC). It provides efficient and scalable communication among the IPs (Intellectual Properties) in a single chip. Mainly, it was introduced to fulfill the growing demand of electronics system which needs to integrate a large number of computational resources into a single chip with an aim to get high performances, And to get efficient performance, the interconnection network plays an important role in chip design. The network architecture or topology should be highly scalable so that it can incorporate a large number of IPs without degrading the performance. In this paper, we proposed a network topology that provides multiple path diversity and high degree of scalability. The architecture of the proposed topology is described along with a packet based adaptive routing algorithm. We simulated the network using an open source simulator named OMNeT++. The topology is tested for average latency, number of events that to be carried in the simulation using a packet based routing algorithm and has been compared with existing Fat tree topology.

A fully grouped routing for Homogeneous FAT Tree Network — On — Chip topology

A routing algorithm plays a critical role in the performance of a Network — on — Chip architecture. An apt routing strategy should cater the performance demands expected from the network, and also the algorithm should be able to scale up seamlessly as the network grows in size. Keeping this in back drop, an attempt is made in this paper to develop a fully grouped routing for Homogeneous Fat Tree Network — On — Chip topology which is both efficient and scalable in nature.