Hsi-Pin Ma

Influence of Non-Alcoholic Fatty Liver Disease on Autonomic Changes Evaluated by the Time Domain, Frequency Domain, and Symbolic Dynamics of Heart Rate Variability

Background Non-alcoholic fatty liver disease (NAFLD) is associated with cardiovascular atherosclerosis independent of classical risk factors. This study investigated the influence of NAFLD on autonomic changes, which is currently unknown. Methods Subjects without an overt history of cardiovascular disease were enrolled during health checkups. The subjects diagnosed for NAFLD using ultrasonography underwent 5-min heart rate variability (HRV) measurements that was analyzed using the following indices: (1) the time domain with the standard deviation of N-N (SDNN) intervals and root mean square of successive differences between adjacent N-N intervals (rMSSD); (2) the frequency domain with low frequency (LF) and high frequency (HF) components; and (3) symbolic dynamics analysis. Routine blood biochemistry data and serum leptin levels were analyzed. Homeostasis model assessment of insulin resistance (HOMA-IR) was measured. Results Of the 497 subjects (mean age, 46.2 years), 176 (35.4%) had NAFLD. The HRV indices (Ln SDNN, Ln rMSSD, Ln LF, and Ln HF) were significantly decreased in the NAFLD group (3.51 vs 3.62 ms, 3.06 vs 3.22 ms, 5.26 vs 5.49 ms2, 4.49 vs 5.21 ms2, respectively, all P<0.05). Ln SDNN was significantly lower in the NAFLD group after adjustment for age, sex, hypertension, dyslipidemia, metabolic syndrome, body mass index, smoking, estimated glomerular filtration rate, HOMA-IR, and leptin (P<0.05). In the symbolic dynamic analysis, 0 V percentage was significantly higher in the NAFLD group (33.8% vs 28.7%, P = 0.001) and significantly correlated with linear HRV indices (Ln SDNN, Ln rMSSD, and Ln HF). Conclusions NAFLD is associated with decreased Ln SDNN and increased 0 V percentage. The former association was independent of conventional cardiovascular risk factors and serum biomarkers (insulin resistance and leptin). Further risk stratification of autonomic dysfunction with falls or cardiovascular diseases by these HRV parameters is required in patients with NAFLD.

A Power-Efficient Configurable Low-Complexity MIMO Detector

In this paper, we propose a power-efficient configurable multiple-input-multiple-output (MIMO) detector, supporting QPSK, 16-QAM, and 64-QAM with low complexity. The approach divides a large MIMO detector into two subsystems: a core detector and a residual detector. The core detector, a low-cost 2 times 2 V-BLAST with ML detector, is used to detect the first two significant outputs. This detector not only efficiently increases the reliability of the entire MIMO detector through its ML performance in mitigating error propagation but also reduces the computational complexity by its search space reduction capability to decrease the computation from O(C 2<) to O(C) (C is the constellation size). The residual detector is an ordered successive interference cancellation (OSIC) detector that detects the rest outputs. The results of bit-error-rate simulations demonstrate that the proposed detector significantly outperforms the OSIC detector. Furthermore, two complete ASIC implementations fabricated by 0.13- mu m 1P8M CMOS technology are presented. We show that the proposed detector, which is configurable from 2 times 2 to 6 times 4 MIMO configurations, has the lowest complexity compared to other fabricated works with 64-QAM demodulation. Moreover, the measured normalized power efficiency of 3.8 Mb/s/mW is shown to be the most power-efficient design compared with the designs of other fabricated works.

A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]

In this paper, an all-digital differentially encoded quaternary phase shift keying (DEQPSK) direct sequence spread-spectrum (DSSS) transceiver is proposed. The transceiver consists of two parts: a baseband/IF spread-spectrum transmitter and a coherent intermediate frequency (IF) receiver. The center frequency of this IF receiver is 11 MHz and the sampling rate is 44 Msamples/s. Modulation/demodulation, carrier recovery, PN acquisition, and differential coding are all provided within a single chip. Functional optimization and architecture design were performed before layout implementation. The 0.8-/spl mu/m N-well CMOS chip has a complexity of 56000 transistors with a core area of 3.5/spl times/3.5 mm/sup 2/. Power dissipation is 92 and 145 mW at 2.6 and 3.3 V, respectively.

A low power ZigBee baseband processor

This paper presents an IEEE 802.15.4 (ZigBee) practicable baseband processor including transmitter and receiver. To estimate and compensate carrier phase error at baseband, the receiver allows full digital solution for carrier phase synchronization. An existing packet detection algorithm for spread spectrum communication system is used to estimate large carrier frequency offset. This paper also presents a new decision-feedback algorithm for residue phase error tracking. The proposed receiver achieves system performance as PER = 0.01 at SNR less than 5 dB, which is better than standard specifications. The baseband processor was implemented in simple hardware architecture and designed with low power technique. The chip is fabricated with the TSMC 0.18 mum 1P6M CMOS technology with a gate count of 78 k. The area is 1.633 mm times 1.633 mm, and power consumption is about 1.7 mW at receiver mode under supply voltage of 1.8 V and operating frequency of 4 MHz.

A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models

Although deep brain stimulation (DBS) has been a promising alternative for treating several neural disorders, the mechanisms underlying the DBS remain not fully understood. As rat models provide the advantage of recording and stimulating different disease-related regions simultaneously, this paper proposes a battery-less, implantable neuro-electronic interface suitable for studying DBS mechanisms with a freely-moving rat. The neuro-electronic interface mainly consists of a microsystem able to interact with eight different brain regions bi-directionally and simultaneously. To minimize the size of the implant, the microsystem receives power and transmits data through a single coil. In addition, particular attention is paid to the capability of recording neural activities right after each stimulation, so as to acquire information on how stimulations modulate neural activities. The microsystem has been fabricated with the standard 0.18 μm CMOS technology. The chip area is 7.74 mm 2, and the microsystem is able to operate with a single supply voltage of 1 V. The wireless interface allows a maximum power of 10 mW to be transmitted together with either uplink or downlink data at a rate of 2 Mbps or 100 kbps, respectively. The input referred noise of recording amplifiers is 1.16 μVrms, and the stimulation voltage is tunable from 1.5 V to 4.5 V with 5-bit resolution. After the electrical functionality of the microsystem is tested, the capability of the microsystem to interface with rat brain is further examined and compared with conventional instruments. All experimental results are presented and discussed in this paper.

Energy efficient diagnostic grade mobile ECG monitoring

An energy efficient prototype for diagnostic grade mobile ECG monitoring is developed. The prototype is developed with commercial discrete components to demo a patient centric medical environment. The prototype uses a mobile phone as a gateway to transmit the measured ECG data back to the medical cloud: Bluetooth for ECG sensor to the mobile phone, while 3G/WiFi for the mobile phone to the medical cloud. Therefore, the patients are not tied to the hospital or home, and can go outside for common life. The prototype can calculate on the mobile phone the RR intervals. More accurate RR, QRS interval can be obtained from server. The platform can also analyze the non-linear analysis of heart rate variability in patients with congestive heart failure based on multi-scale entropy. The size of the developed ECG sensor node is 75 mm × 35 mm × 20 mm which is smaller than a credit card in area. The noise density of the amplifier is 22 nV/√Hz, and the total power of the sensor frontend is below 100 uA. For wireless transmission, the Bluetooth module with a micro controller consumes current less than 110 mA. The prototype can monitor ECG continuously for over 24 hours or with 3 weeks standby time.

A prototype of a wireless-based test system

In this paper, we will describe a prototyping system to demonstrate a next-generation test configuration, which uniformly supports wafer test, final production test and field diagnosis. The implementation shows that we can reduce the test cost significantly by adapting a wireless-based test system.

Optimal Detector for Multitaper Spectrum Estimator in Cognitive Radios

In this paper, the authors propose an optimal detector for the Thomsons multitaper spectral estimation (MTSE) in cognitive radios for spectrum sensing. The MTSE is used for spectral estimation and then the proposed detector can detect primary users and spectrum holes in cognitive radios. The detector is optimized based on the Neyman-Pearson Theorem. The analytical detection performance (probability of detection) of detecting primary users (PUs) and spectrum holes in spectrum sensing is mathematically formulated and verified by simulations. The proposed detector for the MTSE is non-cooperative in spectrum sensing and can perform blind spectrum sensing without prior knowledge of the primary users. Compared to the conventional energy detector, the proposed detector is more reliable and robust for various multiple Slepian tapers. The proposed detector outperforms the cooperative autocorrelation-based detectors in detection rate by 48% and with 3dB gain in SNR performance. Moreover, the minimum required observation size is smaller than the conventional energy detector by a reduction of 73.3%.

A low complexity scalable MIMO detector

A low complexity Multiple-Input Multiple-Output (MIMO) detector with scalability is proposed. The main idea is to divide a large MIMO detector into two parts (core part and residual part), and then the general detection method such as Ordered Successive Interference Cancellation (OSIC) can be applied in each part with smaller dimension. The proposed architecture reduces complexity by avoiding complicated matrix operations in large dimensions. A simplified ML is also proposed in the core part to enhance the detection performance without much complexity. Moreover, the proposed architecture is easily scalable to large MIMO dimensions based on the basic modules. After analysis, the proposed detector outperforms other related researches with lower complexity and has 80% complexity reduction and 5dB performance gain compared with the original Vertical Bell Laboratories Layered Space Time (VBLAST) detector in an 8 x 8 MIMO communication system.

A Power Efficient Baseband Engine for Multiuser Mobile MIMO-OFDMA Communications

In this paper, the authors present a configurable and power efficient multiuser MIMO-OFDMA baseband processor for uplink mobile communications. To solve the carrier frequency offset (CFO) problem in multiuser transmission, an inter-carrier interference-based (ICI-cancellation-based) CFO estimator is implemented based on an iterative search criterion of minimum signal-to-interference-noise (SINR) ratio. Compared to the state-of-the-art methods, the proposed CFO estimator is more robust to transmission configurations (MIMO and multiuser) and CFO variations. Moreover, the authors propose an efficient architecture that saves 78% of the hardware complexity compared to the direct implemented architecture by employing Taylor series expansion for ICI/multiple-access interference (MAI) cancellation. Meanwhile, a 2-D linear channel estimator is also proposed to assist the CFO estimator and track the time-variant multipath channel. Two kinds of MIMO detector, vertical Bell Laboratory layered space-time (V-BLAST) and V-BLAST with maximum likelihood (V-ML), are adopted to minimize output latency and achieve the best ML bit-error-rate (BER) performance. An ASIC fabricated by 0.13 μm 1P8M CMOS technology is measured with 2.31 Mbps/mW power efficiency and less than 1.5 dB implementation loss. In addition, the whole transceiver is integrated and verified by a system-on-chip (SoC) platform to demonstrate its efficacy.