Po-Chiun Huang

Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC

Dynamic element matching (DEM) has been employed to increase the spurious-free dynamic range of data converters. However, generic DEM techniques will induce additional glitch energy. This brief describes a type of the DEM method called random swapping thermometer coding for the implementation of Nyquist-rate current-steering digital-to-analog converters. The selecting direction for a sequence of unit current sources will be randomly changed. Furthermore, combining the restricted jumping technique simultaneously can further smooth low-frequency idle tones. This approach can minimize the number of switched elements as codes change, while achieving good spectrum purity as other DEM implementations. Examples from a behavior-level simulation for 6-bit converters are given to illustrate harmonic suppression and glitch energy improvement achieved by the proposed algorithm.

A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models

Although deep brain stimulation (DBS) has been a promising alternative for treating several neural disorders, the mechanisms underlying the DBS remain not fully understood. As rat models provide the advantage of recording and stimulating different disease-related regions simultaneously, this paper proposes a battery-less, implantable neuro-electronic interface suitable for studying DBS mechanisms with a freely-moving rat. The neuro-electronic interface mainly consists of a microsystem able to interact with eight different brain regions bi-directionally and simultaneously. To minimize the size of the implant, the microsystem receives power and transmits data through a single coil. In addition, particular attention is paid to the capability of recording neural activities right after each stimulation, so as to acquire information on how stimulations modulate neural activities. The microsystem has been fabricated with the standard 0.18 μm CMOS technology. The chip area is 7.74 mm 2, and the microsystem is able to operate with a single supply voltage of 1 V. The wireless interface allows a maximum power of 10 mW to be transmitted together with either uplink or downlink data at a rate of 2 Mbps or 100 kbps, respectively. The input referred noise of recording amplifiers is 1.16 μVrms, and the stimulation voltage is tunable from 1.5 V to 4.5 V with 5-bit resolution. After the electrical functionality of the microsystem is tested, the capability of the microsystem to interface with rat brain is further examined and compared with conventional instruments. All experimental results are presented and discussed in this paper.

An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems

Dynamic voltage and frequency scaling (DVFS) is an effective way for system-level power saving. However, lowering the supply voltage may cause some concerns including yield loss and speed degradation. This paper presents a fully integrated linear regulator that can dynamically assign the supply voltage of a SRAM cell to improve the read and write margins in a DVFS system. To minimize the timing overhead during mode transitions, this design adopts two separate feedback loops for reference tracking and load regulation. Individual loop optimization makes a fast transient response possible. To verify this concept, a prototype regulator without an external component was designed with a 1.8-V 0.18-μm CMOS. The output voltage could be freely set between 0.9-1.7 V. With a 0.1-V step, the measured rising and falling time was within 10 and 35 ns, respectively. The maximum current efficiency was 94.7% under a 20-mA current loading.

A Low Cost Calibrated DAC for High-Resolution Video Display System

This paper presents a digitally enhanced strategy for current-steering digital-to-analog converters (DACs) applied to video systems. The linearity error introduced by the wittingly small current sources is evaluated by an on-chip built-in self-test scheme, which comprises a shared CalDAC, a BiasDAC, and a digital controller. Two current tuning loops are involved for error detection and compensation. Detection range of the current deviation is expanded by utilizing the differential structure and digital signal processor (DSP). For a 12-bit DAC prototype realized in 90-nm CMOS process, about 80% gate area reduction of current source array is achieved compared with the case relying on intrinsic matching only. Measurement results demonstrate that the calibrated converter achieves fully 12-bit linearity with both DNL and INL less than 0.5 LSB. At 400-MS/s update rate, the spurious-free dynamic range is 59 dB within 30 MHz bandwidth.

A Power-Efficient Noise Suppression Technique Using Signal-Nulled Feedback for Low-Noise Wideband Amplifiers

The design of wideband amplifiers suffers from an essential tradeoff between noise and power consumption. This brief presents a power-efficient noise-suppression technique that excludes the signal from a noise-suppression loop by nulling the signal swing in transconductance cells. Once the loop is with less concern on signal linearity, the power constraint on the loop gain stage can be greatly relaxed. Two test circuits have successfully verified this technique. One is an radio-frequency low-noise amplifier (LNA) with the noise figure improved from 5 to 4 dB. The other is a baseband variable-gain amplifier (VGA) with an 11-dB noise reduction. The power overheads for applying the technique in the LNA and the VGA are 0.56 and 0.19 mW, respectively.

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS

Intelligent environments significantly impact human daily lives through embedded sensing and actuating systems. Wireless sensors that can provide non-contact radio information are indispensable. Impulse radar is positioned as a favorable candidate in monitoring and sensing objects [1-3]. The impulse radio is inherently multipath immune and suitable for precision ranging. Accurately detecting signals with low power impulse radios imposes design challenges to impulse radar receivers. In this work, a direct-sampling receiver is proposed and implemented for an impulse radar system. It can support GHz instantaneous bandwidth and more than 100GS/sec equivalent sampling rate through the high-speed sampling circuits and on-chip timing circuitry. The wide bandwidth scattering time-domain waveforms in the radio interaction between the object and radar can be sampled and digitized by the receiver. It achieves precise measurement of time of arrival (TOA) in a radar system and expands the scalability towards antenna arrays for detection of direction of arrival (DOA) [4].

An Integrated 1.2V-to-6V CMOS Charge-Pump for Electret Earphone

This work proposes a new charge pump design that achieves a high set-up ratio for electret earphone driving circuits. The voltage pumping cell is based on Cockcroft-Walton topology to achieve small area with constant MOS capacitor value under low system voltage operation. A 6-V output voltage is regulated by a PFM-based loop. This loop includes a new switched-capacitor divider as a part of the sensing circuitry. All the components are integrated in a standard 0.18 mum CMOS. Measurement results show that with 1.2 V supply, the output voltage is around 6 V with 30 mV output ripple. The maximum output driving current is up to 0.7 mA.

A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensations

This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.

A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range

Current mode control is widely used in the switching power supply designs because of its fast response and less stability concern. However its performance at light load condition is limited by the precision of current sensing. In this work, instead of using high speed current sensor, a frequency-locked loop (FLL) is incorporated to extend the operation range with high power efficiency using a single controller. The 1.8-V output DC-DC converter has been fabricated with a standard 0.35-μm CMOS process and supplied from 2.7 to 4.3 V. Experimental results show that this switching converter operates from 100 to 600 kHz with the efficiency higher than 90% for the load current between 25 and 450 mA. The output voltage ripple is smaller than 30 mV with a 4.7- μH inductor and a 4.7-μF capacitor.

A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops

This paper presents an operational amplifier for a 1-V supply voltage. It comprises three gain stages with ac-boosting and buffered Miller feedback compensation circuits. The implementation uses a standard 0.35-mum CMOS process ( V and V). To accommodate maximum voltage headroom between power rails, a pseudo-differential structure is adopted in this amplifier. The large common-mode gain associated with the structure is suppressed by two common-mode stabilization loops. The amplifier driving 100-pF loads achieves a 4.3-MHz gain-bandwidth product. The settling time of a 1- input step signal is 1.1s. The amplifier consumes 249 muW and occupies 0.06-mm silicon area.