Hsin-i Hu

Characterization of RF Lateral-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors with Different Layout Structures

The DC and RF characteristics of lateral-diffused metal–oxide–semiconductor (LDMOS) transistors with different layout structures were studied. The devices were fabricated using a 0.5 µm LDMOS process. The ring and fishbone structures, which are used widely in power devices, were designed and analyzed. We found that the transconductance, on-resistance, cutoff frequency and maximum oscillation frequency were improved using the ring structure, due to a larger equivalent W/L and lower drain parasitic resistance. In addition, the self-heating effect of LDMOS transistors was also investigated by measuring the pulsed current–voltage (I–V) and pulsed RF characteristics. From the measured results, the ring structure appeared to be a better layout design for RF LDMOS transistors.

A Novel Hybrid Poly-Si Nanowire LDMOS With Extended Drift

A novel hybrid multiple nanowire (NW) channels lateral diffused MOS (LDMOS) with extended drift, which combines the advantages of high breakdown voltage, low specific on-resistance, and superior electrical characteristics is presented. This hybrid NW LDMOS based on polycrystalline silicon thin-film transistor exhibits a high ON/OFF ratio , a low subthreshold slope of 192.6 mV/decade, a high breakdown voltage of 272.6 V, and low specific on-resistance of 161.8 mΩ-cm2.

Temperature-Dependent Capacitance Characteristics of RF LDMOS Transistors With Different Layout Structures

In this letter, the capacitance characteristics of RF LDMOS transistors with different temperatures and layout structures were studied. In a conventional fishbone structure, the peaks in capacitances decrease with increasing temperature. For the ring structure, two peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. In addition, peaks in gate-to-source/body capacitance decrease and peaks in gate-to-drain capacitance increase with increasing temperature at high drain voltages. By analyzing the effects of temperature on threshold voltage, quasi-saturation current, and drift depletion capacitance, the variations of capacitances with temperature were investigated.

Low-Frequency Noise in SONOS-TFT With a Trigate Nanowire Structure Under Program/Erase Operation

This letter investigates low-frequency noise (LFN) in polycrystalline silicon thin-film transistor (TFT) nonvolatile memory (NVM) under Fowler-Nordheim tunneling program/erase (P/E) operation. The NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type structure with a trigate multiple nanowire (NW) channels. The difference in the flicker noise (1/f) level between a multiple-channel NW device and a standard single-channel device became smaller after P/E cycling. The observation can be explained by the quantity of grain-boundary traps introduced by higher electric field at the NW corner during the P/E cycle, subsequently increasing the LFN level in the multiple NW SONOS-TFT.

Low-Frequency Noise in Poly-Si TFT SONOS Memory With a Trigate Nanowire Structure

Low-frequency noise (LFN) in silicon-oxide-nitride-oxide-silicon (SONOS)-type memory that is based on trigate polycrystalline silicon thin-film transistors (TFTs) with a multiple nanowire (NW) channel structure was investigated. The flicker noise level in a multiple NW channel structure was lower than that in a standard single-channel device. The observation could be explained by the fewer grain boundaries in the nanoscale multiple channels, comparable to the grain size, and consequently lowers the impact of LFN in a SONOS-TFT.

High-Frequency Performance of Trigate Poly-Si Thin-Film Transistors by Microwave Annealing

This letter investigates the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) using low temperature microwave annealing (MWA). MWA exhibits sufficient dopant activation efficiency, good short channel effect control, and a higher maximum oscillation frequency (fmax) of poly-Si TFTs than does rapid thermal annealing. In addition, MWA can fabricate nanoscale devices. Poly-Si TFTs with short channel annealed by microwave reveals better high-frequency performance and switching characteristics.

Analysis of Temperature Effects on High-Frequency Characteristics of RF Lateral-Diffused Metal–Oxide–Semiconductor Transistors

In this work, the effects of temperature on the DC and RF characteristics of lateral-diffused metal–oxide–semiconductor (LDMOS) transistors were studied. Devices with different layout structures were fabricated using a 40 V LDMOS process. The temperature coefficients of the threshold voltage and channel mobility are negative and their values are similar for devices with fishbone and ring structures. In addition, we found that both the cutoff frequency ( fT) and the maximum oscillation frequency ( fmax) decrease with increasing temperature. The variations of fT with different temperatures are not only affected by the change in transconductance but also affected by the drain resistance. Finally, the temperature behaviors of S-parameters were measured, and the ring structure showed less S22 variation with different temperatures than the fishbone structure. We extracted the model parameters of the devices to explain this observation. [DOI: 10.1143/JJAP.47.2650]

Novel Poly-Si SJ-LDMOS for System-on-Panel Applications

A superjunction lateral doubled-diffused MOSFET (SJ-LDMOS) that is based on thin-film transistor technology is proposed. To optimize the breakdown voltage (VBD) and specific ON-resistance (RSP), a new structure called TRI-SJ LDMOS, with a triangular p-pillar and an extended trapezoidal n+ region, was designed. The TRI-SJ LDMOS has not only a better VBD than the conventional SJ LDMOS structure on account of its more uniform electric field distribution in the OFF-state, but also a lower RSP on account of the higher current flow in the ON-state. Accordingly, the excellent high-voltage performance of the new polycrystalline silicon TRI-SJ LDMOS makes it a promising candidate for system-on-panel applications.

Effects of Channel Width on High-Frequency Characteristics of Trigate Poly-Si Thin-Film Transistors Fabricated by Microwave Annealing

In this paper, the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) is analyzed using low-temperature microwave annealing. The variation of the cutoff frequency and the maximum oscillation frequency with the width of the channel wire is investigated. A poly-Si TFT with a short channel and a narrow channel wire, annealed using microwave, has a high driving current, a good gate controllability, and a better high-frequency performance than one that annealed by rapid thermal annealing.

Novel Gate-All-Around High-Voltage Thin-Film Transistor With T-Shaped Metal Field Plate Design

A novel gate-all-around (GAA) high-voltage thin-film transistor (HVTFT) with the T-shaped metal field plate (MFP) design results in a high breakdown voltage (V_BD) of 119.9 V and a low specific ON-resistance (R_SP) of 8.4 mQ · cm². This T-shaped MFP GAA HVTFT solves the V_BD-R_SP tradeoff problems and exhibits superior gate control performance, which leads to excellent electrical characteristics such as a better ON/OFF ratio of >10¹⁰ and a lower subthreshold slope of 154.4 mV/decade than the conventional planar structure.