Hsin-Lei Lin

A High-Speed SDM-MIMO Decoder Using Efficient Candidate Searching for Wireless Communication

In this brief, a high-speed space-division multiplexing (SDM) multiple-input-multiple output (MIMO) decoder using efficient candidate searching is proposed by exploiting the characteristics of QR decomposition and sphere decoder for high throughput rate and low hardware-complexity. A process of efficient candidate searching by shifting the center of constellation with scalable radius reduces the processing time and improves the operational frequency. The proposed architecture can operate at a 166-MHz clock frequency, and the core area is smaller than results from using the K-best SD algorithm since large memory is not required to store extreme candidate paths. In our implementation, the core area is 0.675 mm using TSMC 90-nm technology. The average throughput of the proposed SDM-MIMO decoder is 95 Mbps with 64-QAM modulation at 30-dB signal-to-noise ratio.

Implementation of digital IQ imbalance compensation in OFDM WLAN receivers

Although the maximum transmission speed in IEEE 802.11a WLAN is 54 Mbps, the real throughput is actually limited to 20~30 Mbps. Except for the main effect from multi-path, we should also consider some non-ideal effects from imperfect hardware design, such as the IQ imbalance from direct conversion in RF front-end. IQ imbalance is not apparent in lower-order QAM modulation. However, in higher-order QAM modulation, it will become serious interference. In this paper, an IQ imbalance compensation circuit in IEEE802.11a baseband receiver is proposed. A low complexity time-domain compensation algorithm is used to replace the traditional high-order equalizer. MATLAB is used to simulate the whole transceiver including the channel model. After system verification, we use Verilog to implement the IQ imbalance compensation circuit with UMC 0.18 mum CMOS 1p6m technology. Post-layout simulation results show that this scheme contributes to a very robust and easily implemented OFDM WLAN receiver

Implementation of synchronization for 2x2 MIMO WLAN system

This work presents a novel synchronization architecture for a 2times2 MIMO OFDM WLAN system. A new CORDIC-based sinusoidal iterative oscillator architecture is also implemented to recover the carrier frequency. The proposed design mainly enhances the traditional digital oscillator, which is a CORDIC-based architecture, and which is adopted at each accumulated phase. Compared to the iterative CORDIC computation, the proposed CORDIC-based sinusoidal iterative oscillator architecture operates the CORDIC only once. Moreover, the timing controller negotiates these two antenna input signals, and gates the useless signal to lower the power consumption. The proposed architecture with high precision is simulated and emulated by 0.18 mum 1P6M CMOS technology and FPGA respectively

Design of a novel radix-4 booth multiplier

This paper presents a novel radix-4 Booth multiplier. A conventional Booth multiplier consists of the Booth encoder, the partial-product summation tree, and the canypropagate adder. Different schemes are addressed to improve the area and circuit speed effectively. A novel modified Booth encodeddecoder is proposed and the summation column is compressed by the proposed MFAr. The proposed design is simulated by Synopsys and Apollo. It results 20% area reduction, 17%&-24% power decrease, and 15% reduction of the delay time of the critical path.

A novel pipelined fast Fourier transform architecture for double rate OFDM systems

A high throughput fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) processor for double-rate wireless LAN, based on double-rate OFDM communication systems, is proposed. It is an efficiently pipelined radix-2 FFT architecture, which doubles the throughput with significant hardware reduction. The utilization rate of multipliers and the processing elements reach 100%. The core size is 10 mm/sup 2/ with a power consumption of 208 mW at 20 MHz for data inputs with 15-bit word length, using 0.35 /spl mu/m IP4M CMOS technology.

Analysis and Architecture Design of a Downlink

This paper investigates the feasibility of applying Tomlinson-Harashima precoding (THP) to multicarrier code-division multiple-access (MC-CDMA) system downlinks, in which multiple-access interference and possible complexity in the mobile terminal (MT) are major burdens. A THP based on the minimum mean-square error (MMSE) criterion is also presented, making it possible to realize a low-complexity receiver at the MT. The hardware architecture of the MMSE THP with modified QR decomposition at the transmitter is presented, along with the required word length analyzed. Pipeline and parallel schemes are adopted to reduce the execution time. For a generic square matrix of order for RQ decomposition, the required latency is time units, which is based on the modified Gram-Schmidt algorithm.

M

A high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18mum 1P6M technology at supply voltage of 1.8V

-Modification MC-CDMA System Using the Tomlinson–Harashima Precoding Technique

A detection of joint QR decomposition and partial sphere decoder (JQRPSD) method with low complexity is proposed in this paper. The purpose of the detection is reducing complexity from sphere decoder and having better performance than successive cancellation detection with QR decomposition (QR-SCD) and vertical Bell laboratories layered space-time (V-BLAST). In a perfect channel estimated receiver, the simulation of JQRPSD method performs the performance approaching the performance of sphere decoder algorithm. The proposed detector is designed by TSMC 0.18 mum CMOS technology without preprocessor in 4 x 4 multiple input and multiple output (MIMO) wireless communication.

A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

In this paper, Tomlinson-Harashima precoding (THP) algorithm for the downlink of MC-CDMA system, in which multiple-access interference and possible complexity in the mobile terminal are major burdens, is investigated. A new THP based on the minimum mean-square error (MMSE) criterion is derived. It has the better performance than the zero forcing (ZF) THP. The authors proposed the hardware architecture of MMSE THP at the transmitter and analyzed the required word length. The pipeline and parallel processes are employed to efficiently save time of executing procedure

JQRPSD Detection with Low Complexity for SDM MIMO Wireless Communication System

In the wireless mobile communication system, a decision feedback equalizer (DFE) to cancel the inter symbol interference (ISI) is required. This paper analyzes and implements the decision feedback equalizer and a novel CCK architecture of the receiver. All the filters are implemented using the finite impulse response (FIR) filter. The least mean square (LMS) algorithm with initial values is used for updating the coefficient as fast as it can be in the parallel DFE architecture. The area requirement of the novel CCK demodulator structure is about half of that of Fast Walsh Block structure, while their delay times are approximately the same. After synthesis, the total gate counts of the DFE and the CCK demodulator are 58624 and 9937, respectively. The power consumption of DFE is 25.087 mW operating under a 3.3 V supply voltage.