Hu Aibin

(NH4)2S treatment of the Si (100) surface and its effects on Al/Si Schottky barrier heights

The effect of Si (100) surface S passivation was investigated. A thick film with a high roughness value was formed on the Si surface treated by (NH4)2S solution, which was attributed to physical adsorption of S atoms. SEM and XPS analyses reveal that Si surface atoms were chemically bonded with S atoms after Si surface treatment in NH4OH and (NH4)2S mixing solution. This induces a more ideal value for the Schottky barrier height compared with a diode treated only by HF solution, indicating that surface states originating from dangling bonds are passivated with S atoms.

SPT+-IGBT characteristics and optimization

A novel advanced soft punch through (SPT) IGBT signed as SPT+-IGBT is investigated. Static and dynamic characteristics are simulated based on the 1200 V device structure and adopted technology. Extensive research on the structure optimization of SPT+-IGBT is presented and discussed. Compared with the structure of conventional IGBT, SPT+-IGBT has a much lower collector—emitter saturation voltage and better switching characteristics. Therefore it is very suitable for applications blocking a voltage higher than 3000 V. In addition, due to the improvement of switching speed achieved by using a thinner chip, SPT+-IGBT is also very competitive in 1200 V and 1700 V applications.

Effects of silicon nitride diffusion barrier on germanium MOS capacitors with HfON gate dielectrics

MOS capacitors with hafnium oxynitride (HfON) gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method. A large amount of fixed charges and interface traps exist at the Ge/HfON interface. HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing. A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier. Using this method, well behaved capacitance-voltage and current-voltage characteristics were obtained. Finally hystereses are compared under different process conditions and possible causes are discussed.

Comparative studies of Ge and Si p-channel metal－oxide－semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal–oxide–semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance–voltage curve hysteresis of Ge metal–oxide–semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.