Lu Shuojin

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range (-55 to 150 C). An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Discussion on the relationship between Δ V_(EB) and I_E presented in thermal resistance standard IEC60747-7 Version 2000

This paper points out an error in the principle figure and the waveform figure of the thermal resistance standard IEC747-7, which describes the relation between the I-V curves and the temperature. It theoretically proves that the I-VT curve of the standard contradicts the physical law. This contradiction is also revealed by experimental results. Finally, the correct I-VT characteristic curve and the waveform figure at two different temperatures for the same transistor is given, which serves as the reference to correct the standard. Supported by the National Natural Science Foundation of China (Grant No. 60476039)

A novel optimization design for 3.3 kV injection-enhanced gate transistor

This paper introduces a homemade injection-enhanced gate transistor (IEGT) with blocking voltage up to 3.7 kV. An advanced cell structure with dummy trench and a large cell pitch is adopted in the IEGT. The carrier concentration at the N-emitter side is increased by the larger cell pitch of the IEGT and it enhances the P—i—N effect within the device. The result shows that the IEGT has a remarkablely low on-state forward voltage drop (VCE(sat)) compared to traditional trench IGBT structures. However, too large cell pitch decreases the channel density of the trench IEGT and increases the voltage drop across the channel, finally it will increase the VCE(sat) of the IEGT. Therefore, the cell pitch selection is the key parameter consideration in the design of the IEGT. In this paper, a cell pitch selection method and the optimal value of 3.3 kV IEGT are presented by simulations and experimental results.

Influence of body contact of SOI MOSFETs on the thermal conductance of devices

The thermal conductance of devices with different body contacts is studied. A new analytical expression is proposed. This expression can be used in parameter extraction, which gives both good efficiency and high precision. The ratio of thermal conductance of the body contact region to that of the body region is nearly equal to the ratio of the area. The use of an H shape gate body contact is suggested to aid power dissipation in SOI MOSFETs.

Influence of electron irradiation on the switching speed in insulated gate bipolar transistors

The influence of electron irradiation on the switching speed in insulated gate bipolar transistors (IGBT) with different epitaxial layer thicknesses is discussed in detail. The experimental results prove that the fall time of IGBT increases when increasing the thickness of the epitaxial layer. However, there is no obvious difference between the ratios of the fall time after irradiation to those before irradiation for different epitaxial layer thicknesses. The increase in switching speed of the IGBT is accompanied by an increase in the forward drop, and a trade-off curve between forward voltage drop and fall time of IGBT is presented.

A novel high performance SemiSJ-CSTBT with p-pillar under the bottom of the trench gate*

A novel high performance SemiSJ-CSTBT is proposed with the p-pillar under the bottom of the trench gate. The inserted p-pillar with the neighbouring n-drift region forms a lateral P/N junction, which can adjust the electric distribution in the forward-blocking mode to achieve a higher breakdown voltage compared to the conventional CSTBT. Also, the p-pillar can act as a hole collector at turn-off, which significantly enhances the turn-off speed and obtains a lower turn-off switching loss. Although the turn-off switching loss decreases as the depth of the p-pillar increases, there is no need for a very deep p-pillar. The associated voltage overshoot at turn-off increases dramatically with increasing the depth of p-pillar, which may cause destruction of the devices. Plus, this will add difficulty and cost to the manufacturing process of this new structure. Therefore, the proposed SemiSJ-CSTBT offers considerably better robustness compared to the conventional CSTBT and SJ-CSTBT. The simulation results show that the SemiSJ-CSTBT exhibits an increase in breakdown voltage by 160 V (13%) and a reduction of turn-off switching loss by approximately 15%.

4500 V SPT+ IGBT optimization on static and dynamic losses*

This paper concerns the need for improving the static and dynamic performance of the high voltage insulated gate bipolar transistor (HV IGBTs). A novel structure with a carrier stored layer on the cathode side, known as an enhanced planar IGBT of the 4500 V voltage class is investigated. With the adoption of a soft punch through (SPT) concept as the vertical structure and an enhanced planar concept as the top structure, signed as SPT+ IGBT, the simulation results indicate the turn-off switching waveform of the 4500 V SPT+ IGBT is soft and also realizes an improved trade-off relationship between on-state voltage drop (Von) and turn-off loss (Eoff) in comparison with the SPT IGBT. Attention is also paid to the influences caused by different carrier stored layer doping dose on static and dynamic performances, to optimize on-state and switching losses of SPT+ IGBT.

Backside optimization for improving avalanche breakdown behavior of 4.5 kV IGBT

The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N+ buffer layer, the other is decreasing the implant dose of the P+ collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.