Zhu Yangjun

A simulation study on a novel trench SJIGBT

An overall analysis of the trench superjunction insulated gate bipolar transistor (SJ IGBT) is presented and a detailed comparison between a trench SJ IGBT and a trench field stop IGBT is made by simulating with Sentaurus TCAD. More specifically, simulation results show that the trench SJ IGBT exhibits a breakdown voltage that is raised by 100 V while the on-state voltage is reduced by 0.2 V. At the same time, the turn-off loss is decreased by 50%. The effect of charge imbalance on the static and dynamic characteristics of the trench SJ IGBT is studied, and the trade-off between parameters and their sensitivity versus charge imbalance is discussed.

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

SPT+-IGBT characteristics and optimization

A novel advanced soft punch through (SPT) IGBT signed as SPT+-IGBT is investigated. Static and dynamic characteristics are simulated based on the 1200 V device structure and adopted technology. Extensive research on the structure optimization of SPT+-IGBT is presented and discussed. Compared with the structure of conventional IGBT, SPT+-IGBT has a much lower collector—emitter saturation voltage and better switching characteristics. Therefore it is very suitable for applications blocking a voltage higher than 3000 V. In addition, due to the improvement of switching speed achieved by using a thinner chip, SPT+-IGBT is also very competitive in 1200 V and 1700 V applications.

The snap-back effect of an RC-IGBT and its simulations

The RC-IGBT (reverse conducting insulated gate bipolar transistor) is a new kind of power semiconductor device which has many advantages such as smaller chip size, higher power density, lower manufacturing cost, softer turn off behavior, and better reliability. However, its performance has a number of drawbacks, such as the snap-back effect. In this paper, an introduction about the snap-back effect of the RC-IGBT is given firstly. Then the physical explanations are presented with two simplified models. After that, some numerical simulations are carried out to verify the correctness of the models.

Discussion on the relationship between Δ V_(EB) and I_E presented in thermal resistance standard IEC60747-7 Version 2000

This paper points out an error in the principle figure and the waveform figure of the thermal resistance standard IEC747-7, which describes the relation between the I-V curves and the temperature. It theoretically proves that the I-VT curve of the standard contradicts the physical law. This contradiction is also revealed by experimental results. Finally, the correct I-VT characteristic curve and the waveform figure at two different temperatures for the same transistor is given, which serves as the reference to correct the standard. Supported by the National Natural Science Foundation of China (Grant No. 60476039)

A novel optimization design for 3.3 kV injection-enhanced gate transistor

This paper introduces a homemade injection-enhanced gate transistor (IEGT) with blocking voltage up to 3.7 kV. An advanced cell structure with dummy trench and a large cell pitch is adopted in the IEGT. The carrier concentration at the N-emitter side is increased by the larger cell pitch of the IEGT and it enhances the P—i—N effect within the device. The result shows that the IEGT has a remarkablely low on-state forward voltage drop (VCE(sat)) compared to traditional trench IGBT structures. However, too large cell pitch decreases the channel density of the trench IEGT and increases the voltage drop across the channel, finally it will increase the VCE(sat) of the IEGT. Therefore, the cell pitch selection is the key parameter consideration in the design of the IEGT. In this paper, a cell pitch selection method and the optimal value of 3.3 kV IEGT are presented by simulations and experimental results.

A novel high performance SemiSJ-CSTBT with p-pillar under the bottom of the trench gate*

A novel high performance SemiSJ-CSTBT is proposed with the p-pillar under the bottom of the trench gate. The inserted p-pillar with the neighbouring n-drift region forms a lateral P/N junction, which can adjust the electric distribution in the forward-blocking mode to achieve a higher breakdown voltage compared to the conventional CSTBT. Also, the p-pillar can act as a hole collector at turn-off, which significantly enhances the turn-off speed and obtains a lower turn-off switching loss. Although the turn-off switching loss decreases as the depth of the p-pillar increases, there is no need for a very deep p-pillar. The associated voltage overshoot at turn-off increases dramatically with increasing the depth of p-pillar, which may cause destruction of the devices. Plus, this will add difficulty and cost to the manufacturing process of this new structure. Therefore, the proposed SemiSJ-CSTBT offers considerably better robustness compared to the conventional CSTBT and SJ-CSTBT. The simulation results show that the SemiSJ-CSTBT exhibits an increase in breakdown voltage by 160 V (13%) and a reduction of turn-off switching loss by approximately 15%.

4500 V SPT+ IGBT optimization on static and dynamic losses*

This paper concerns the need for improving the static and dynamic performance of the high voltage insulated gate bipolar transistor (HV IGBTs). A novel structure with a carrier stored layer on the cathode side, known as an enhanced planar IGBT of the 4500 V voltage class is investigated. With the adoption of a soft punch through (SPT) concept as the vertical structure and an enhanced planar concept as the top structure, signed as SPT+ IGBT, the simulation results indicate the turn-off switching waveform of the 4500 V SPT+ IGBT is soft and also realizes an improved trade-off relationship between on-state voltage drop (Von) and turn-off loss (Eoff) in comparison with the SPT IGBT. Attention is also paid to the influences caused by different carrier stored layer doping dose on static and dynamic performances, to optimize on-state and switching losses of SPT+ IGBT.

Backside optimization for improving avalanche breakdown behavior of 4.5 kV IGBT

The static avalanche breakdown behavior of 4.5 kV high-voltage IGBT is studied by theory analysis and experiment. The avalanche breakdown behaviors of the 4.5 kV IGBTs with different backside structures are investigated and compared by using the curve tracer. The results show that the snap back behavior of the breakdown waveform is related to the bipolar PNP gain, which leads to the deterioration of the breakdown voltage. There are two ways to optimize the backside structure, one is increasing the implant dose of the N+ buffer layer, the other is decreasing the implant dose of the P+ collector layer. It is found that the optimized structure is effective in suppressing the snap back behavior and improving the breakdown characteristic of high voltage IGBT.

A novel electrical measurement method of peak junction temperature based on the excessive thermotaxis effect of low current

It has been a scientific and technological problem in the field of microelectronics for several decades that the electrical method is used to measure the peak junction temperature of power transistors. Based on the excessive thermotaxis effect of low current, a novel electrical measurement method of the peak junction temperature is presented in this paper. The method is called the thermal spectrum analysis method of transistors, simply designated TSA (thermal spectrum analysis method). Unlike the common method which uses a single measuring current, TSA uses multi-step currents to measure temperature-sensitive parameters. Based on the excessive thermotaxis effect of low current and the sub-transistor parallel model, the peak junction temperature and non-uniform property of junction temperature distribution are analyzed successfully.