Hu Shengdong

A 50?60 V Class Ultralow Specific on-Resistance Trench Power MOSFET

A 50–60 V class ultralow specific on-resistance (Ron,sp) trench power MOSFET is proposed. The structure is characterized by an n+-layer which is buried on the top surface of the p-substrate and connected to the drain n+-region. The low-resistance n+-layer shortens the motion-path in high-resistance n− drift region for the carriers, and therefore, reduces the Ron,sp in the on-state. Electrical characteristics for the proposed power MOSFET are analyzed and discussed. The 50–60 V class breakdown voltages (VB) with Ron,sp less than 0.35 mΩcm2 are obtained. Compared with several power MOSFETs, the proposed power MOSFET has a significantly optimized dependence of Ron,sp on VB.

Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device

A 1200-V thin-silicon-layer p-channel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor is designed. The device named INI SOI p-LDMOS is characterized by a series of equidistant high concentration n+ islands inserted at the interface of a top silicon layer and a buried oxide layer. Accumulation-mode holes, caused by the electric potential dispersion between the device surface and the substrate, are located in the spacing between two neighboring n+ islands, and greatly enhance the electric field of the buried oxide layer and therefore, effectively increase the device breakdown voltage. Based on a 2-μm-thick buried oxide layer and a 1.5-μm-thick top silicon layer, a breakdown voltage of 1224 V is obtained, resulting in the high electric field (608 V/μm) of the buried oxide layer.

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (EI) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region. This results in the enhancement of the breakdown voltage (BV). The values of EI and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and −582 V, respectively, compared with 81.5 V/μm and −123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance *

A novel silicon-on-insulator (SOI) power metal-oxide-semiconductor field effect transistor with an interface-gate (IG SOI) structure is proposed, in which the trench polysilicon gate extends into the buried oxide layer (BOX) at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n+-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (EI), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 ?m) and BOX (0.375 ?m), the EI and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n+-layer

A novel partial silicon-on-insulator laterally double-diffused metal—oxide—semiconductor transistor (PSOI LDMOS) with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n+-layer, which is partially buried on the bottom interface of the top silicon layer (PBNL PSOI LDMOS). The undepleted interface n+-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage (BV). With the same thickness values of the top silicon layer (10 μm) and buried oxide layer (0.375 μm), the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.