Li Zhaoji

A New CMOS Current Reference with High Order Temperature Compensation

A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 mum standard CMOS technology, gives a good temperature coefficient of 31 ppm/degC [-50~100degC] at a 1.8 V supply, and also achieves line regulation of 0.01%/V and -120 dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and line regulation

A 700 V BCD technology platform for high voltage applications

A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mΩ·cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.

Fuzzy pulse skip modulation mode in DC-DC converter

This paper presents the FPSM (fuzzy pulse skip modulation) mode in DC-DC converter, which bases on PSM (pulse skip modulation) mode proposed by author recently. This paper gives the structure, fuzzy rule and simulation results of FPSM. It is shown that FPSM converter not only has high efficiency, quick response and strong robust characteristics comparing with PSM converter, but also has low output voltage ripple and can escape from audible noise range.

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors (MESFETs) with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.

Analysis of the Stability and Ripple of PSM Converter in DCM by EB Model

Based on the theory of energy conservation, the Energy Balance (EB) model of a PSM (Pulse Skip Modulation) converter in DCM (Discontinuous Current Mode) is proposed in this paper. The relationships of the output voltage versus modulation factor M and load resistances R are given. The stability of a PSM converter in DCM is analyzed based on this proposed EB model. Simulation results show that chaos never occurs but bifurcations happen for a PSM converter in DCM. The PSM converter will be stable at either period-(n+m) bifurcation mono-cycle stabilization or (ni +mi) multi-cycle stabilization. ni=1 or mi=1 always occurring whenever a PSM converter operating in DCM is proved by simulation. The boundary resistances of period-(n+m) bifurcation and the output voltage ripples are also given in this paper.

A High Figure-of-Merit SOI MOSFET with a Double-Sided Charge Oxide-Trench

A novel silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with a high figure of merit (FOM) is proposed. The device features a double-sided charge oxide-trench (DCT) and a trench gate extended to the buried oxide. First, the oxide trench causes multiple-dimensional depletion in the drift region, which not only improves the electric field (E-field) strength, but also enhances the reduced surface field effect. Second, self-adaptive charges are collected in the DCT, which enhances the E-field strength of the trench oxide. Third, the oxide trench folds the drift region along the vertical direction, reducing the device cell pitch. Fourth, one side of the DCT regions acts as the body contact of p-well to reduce cell pitch and specific on-resistance (Ron,sp) further. Compared with a trench gate lateral double-diffused MOSFET, the DCT MOSFET increases the breakdown voltage (BV) from 53 V to 158 V at the same cell pitch of 3.5 μm, or reduces the cell pitch by 60% and Ron,sp by 70% at the same BV. The FOM (FOM=BV2/Ron,sp) of the proposed structure is 23 MW/cm2.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (Ron,sp) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and Ron,sp of 0.985 mΩ·cm2 (VGS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, Ron,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.

Study for safe operating area of high voltage LDMOS

An analytical on-state breakdown model for high voltage RESURF LDMOS has been proposed in this paper. The model considers the drift velocity saturation of carriers and influence of the parasitic bipolar transistor. As a result, the electric field profile of n-drift in LDMOS, in the on-state, can be obtained. Based on this model, the safe operating area (SOA) of LDMOS can be calculated. The analytical results partially fit with our numerical (by MEDICI) and experiment results. This model is an accurate aid in understanding the device physics during the on-state, and it also directs high voltage LDMOS design.