Hu Xu

Analytical heat transfer model for thermal through-silicon vias

Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on the heat transfer process within 3-D ICs is investigated. Two resistive networks are utilized to model the physical behavior of TTSVs. Based on these models, closed-form expressions are provided describing the flow of heat through TTSVs within a 3-D IC. The accuracy of these models is compared with results from a commercial FEM tool. For an investigated three-plane circuit, the average error of the first and second models is 2% and 4%, respectively. The effect of the physical parameters of TTSVs on the resulting temperature is described through the proposed models. For example, the temperature changes non-monotonically with the thickness of the silicon substrate. This behavior is not described by the traditional single thermal resistance model. The proposed models are used for the thermal analysis of a 3-D DRAM-μP system where the conventional model is shown to considerably overestimate the temperature of the system.

The combined effect of process variations and power supply noise on clock skew and jitter

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.

Process-induced skew variation for scaled 2-D and 3-D ICs

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented at scaled technology nodes and for a 3-D circuit with an increasing number of planes is investigated in this paper. An accurate model used to describe the effect of the proper sources of variations on each of these design approaches is proposed. The distribution of the pair-wise skew variation is obtained for single scaled or multi-plane (not scaled) clock distribution networks. The accuracy of the presented statistical skew model is verified through Monte-Carlo simulations. As shown in this paper, the clock skew variation due to technology scaling and/or die stacking exhibits a considerably different behavior. A comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency. A popular global clock tree topology is employed in a planar (2-D) circuit where technology scaling is applied and in a 3-D circuit with an increasing number of planes. For this clock tree topology, the maximum supported clock frequency increases from 2.75 GHz to 3.74 GHz by proper die-stacking at a 90 nm technology node. 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling.

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown to be underestimated up to 36% if process variations and dynamic power supply noise are considered separately, which highlights the importance of this unified treatment. Potential scenarios of supply noise in 3-D integrated circuits (ICs) are investigated. 3-D circuits generated from industrial benchmarks are simulated to show the skitter under these scenarios. The mean and standard deviation of skitter can vary up to 60% and 51%, respectively, due to the different amplitudes and phases of supply noise. The tradeoff between skitter and the power consumed by clock trees is also shown. A set of guidelines are presented to decrease skitter in 3-D ICs. By applying these guidelines to industrial benchmarks, simulations show a decrease in the mean skitter up to 31%.

Effect of process variations in 3D global clock distribution networks

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

Skew variability in 3-D ICs with multiple clock domains

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock distribution networks. A statistical clock skew model incorporating spatially correlated intra-die process variations is employed to describe this effect. The clock skew is shown to change in different ways with the allocation of the clock domains within the 3-D circuit. Various schemes to assign the clock domains are investigated. Different scenarios of inter-die and intra-die process variations and an intra-die spatial correlation model are applied to these schemes. An approach where each physical plane corresponds to a single clock domain is shown to be inferior to other clocking schemes for specific variation scenarios. Tradeoffs between the number of clock domains within a physical plane and the number of planes a clock tree spans are discussed and related design guidelines are offered.

Synchronization and power integrity issues in 3-D ICs

Several challenges should be resolved for three-dimensional integration to evolve to a mainstream technology. Among these challenges, the issues of synchronization and power integrity become predominant due to the multiple planes and the heterogeneity of 3-D circuits. The paper offers an overview of the state of the art research related to these global in nature issues. Experimental results, design techniques, and models are discussed highlighting the possible means and requirements for the design of reliable synchronization and power distribution schemes in 3-D circuits.

Enhanced wafer matching heuristics for 3-D ICs

Summary form only given. Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs. The data obtained during this step can guide the subsequent manufacturing stages to improve the functional or parametric yield of the 3-D stack. The existing methods, however, do not relate directly the performance of the resulting circuits with sales revenues. More importantly, methods that consider the distribution of speed of the assembled 3-D stacks neglect the partition of the critical path delay across the layers of the stack. In other words, a physical layer that does not include any critical path does not primarily determine the performance of the system. Consequently, for a method that aims at maximizing the profit that can be made from a 3-D system, this layer should be treated differently.

Effects of Process Variations on 3-D Global Clock Distribution Networks

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.