Hu Yongcai

A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector*

An on-chip reference voltage has been designed in capacitor–resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μm 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80 °C, the temperature coefficient is 12.2 ppm/°C. The PSRR was −70 dB @ 100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449 × 614 μm2. The total power consumption is only 1.092 mW.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors*

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e− at zero farad plus 8.2 e− per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).

A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors*

This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for multi-channel CdZnTe (CZT) detector applications. In order to improve the SAR-ADCs accuracy, a novel comparator is proposed in which the offset voltage is self-calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm2.