Wei Tingcun

A high-resolution multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications

This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay-locked loops is proposed for fine conversion. The resolution range is achieved from 71 ps to 142 ps by use of a reference clock from 100 MHz to 50 MHz. The measured range of the TDC is 10 µs. A prototype chip of 3-channel TDC for PET imaging system is designed and fabricated in AMS 0.35 µm CMOS technology. The area of the chip is 8.4 mm2 in size. The differential nonlinearity is ±0.1 LSB. The integral nonlinearity is ±0.1 LSB. The circuits will be extended to 64 channels for small animal PET imaging system.

Modeling of pinned photodiode for CMOS image sensor

Photodetector is the very important part of CMOS image sensors. At present, the pinned photodiodes (PPDs) are popularly used in photon-to-electricity conversion process, which can minish the dark current greatly. Therefore, it is important and necessary to construct an accurate and reasonable model before conducting research on the structure of CMOS image sensor. Here the study utilizes the minority carrier equilibrium continuity equations and semiconductor material absorption of photon to get the expression of photocurrent. By means of MATLAB, the relationship between responsibility and wavelength of pinned photodiode is found out and the results are analyzed. Finally, the model is proved to be effective by comparing the results of this model with another simulation results by Taurus Medici 2003 and Taurus Tsuprem 4.

A reference voltage in capacitor–resister hybrid SAR ADC for front-end readout system of CZT detector*

An on-chip reference voltage has been designed in capacitor–resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μm 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80 °C, the temperature coefficient is 12.2 ppm/°C. The PSRR was −70 dB @ 100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449 × 614 μm2. The total power consumption is only 1.092 mW.

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors*

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e− at zero farad plus 8.2 e− per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).

A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors*

This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for multi-channel CdZnTe (CZT) detector applications. In order to improve the SAR-ADCs accuracy, a novel comparator is proposed in which the offset voltage is self-calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm2.

A novel DPWM structure with high time resolution and low clock frequency

This paper presents a novel digital pulse width modulator (DPWM) structure with higher time resolution and lower input clock frequency, which is especially suitable for high frequency digitally controlled DC-DC switching converters. For the proposed DPWM, two multi-phase clock arrays are generated which have relatively close frequencies, and the time-inserting method is also utilized. The FPGA based simulation results show that, the proposed DPWM can achieve the time resolution of around 30ps and the equivalent 12-bits precision when the input dual-clock frequencies are 100MHz and 105MHz at 5MHz switching frequency.

Architecture of the Front-End Readout ASIC for 4-D PET Imaging

Front-end electronic system for PET imaging is a complex analog-digital mixed signal processing system, including detector/sensor, front-end readout electronic chain and digital signal processor, and so on. This paper discussed the necessity, basic circuit architecture, design flow and design challenges of front-end readout ASIC for 4-D biomedical imaging applications. The design trend of this kind of circuits is given in this paper, for which the further researches would head to the mixed-signal ASIC realization of front-end readout system and DSP for appropriative imaging.

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC–DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pumps power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.