Hua-Mao Chen

Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors

This paper investigates the channel hot carrier stress (CHCS) effects on gate-induced drain leakage (GIDL) current in high-k/metal-gate n-type metal-oxide-semiconductor field effect transistors. It was found that the behavior of GIDL current during CHCS is dependent upon the interfacial layer (IL) oxide thickness of high-k/metal-gate stacks. For a thinner IL, the GIDL current gradually decreases during CHCS, a result contrary to that found in a device with thicker IL. Based on the variation of GIDL current at different stress conditions, the trap-assisted band-to-band hole injection model is proposed to explain the different behavior of GIDL current for different IL thicknesses.

Effects of Varied Negative Stop Voltages on Current Self-Compliance in Indium Tin Oxide Resistance Random Access Memory

We have previously investigated the automatic current compliance property for indium tin oxide (ITO) resistance random access memory (RRAM). Traditionally, for the purpose of protecting RRAM, it is necessary to set equipment current compliance during the set and forming processes of RRAM devices. ITO RRAM devices, however, have an intrinsic capability to limit their current. This letter examines this ITO RRAM current compliance in depth by applying a varied stop-voltage measurement method, where different negative stop voltages were adopted to manipulate oxygen ions. Combined with material analysis and conduction current fitting, a model was established.

Physical and Electrical Characterization of ZrO2 Gate Insulators Deposited on Si(100) Using Zr ( O i ­ Pr ) 2 ( thd ) 2 and O 2

The characteristics of ultrathin ZrO 2 films deposited using molecular oxygen and the zirconium precursor Zr(O i - Pr) 2 (thd) 2 [where O i -Pr is isopropoxide and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate] were investigated. The organometallic was dissolved as a 0.15 M solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390-550°C. No evidence of Zr-C and Zr-Si bonds were found in the X-ray photoelectron spectroscopy (XPS), spectra, and carbon concentrations, <0.1 atom %, the detection limit of the XPS depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the ZrO 2 films to be polycrystalline as deposited, with an amorphous zirconium silicate interfacial layer. The effects of postdeposition annealing were also demonstrated. After proper annealing treatments, promising capacitance-voltage and current-voltage characteristics were achieved. A film with an equivalent oxide thickness of 2.3 nm showed current reductions of approximately two orders of magnitude when compared to SiO 2 , but some improvements are required if these films are to be used as a gale-insulator beyond the 100 nm CMOS (complementary metal oxide semiconductor) technology node.

X-Ray Photoelectron Spectroscopy of Gate-Quality Silicon Oxynitride Films Produced by Annealing Plasma-Nitrided Si(100) in Nitrous Oxide

cNational Nano-Device Laboratories, Hsinchu 300, Taiwan Ultrathin silicon oxynitride films with thickness in the range of 1.8-3.5 nm have been produced on Si~100! by nitridation of an NO-oxidized surface with an electron-cyclotron resonance plasma source. The films were annealed in N 2O at 950°C for times up to 60 s and formed into Al-gated capacitors for capacitance-voltage ~CV! and current-voltage analysis. The rapid annealing increases the oxygen content of the films but results in capacitors with excellent electrical properties. For a plasma oxynitride with equivalent oxide thickness, t eq 5 1.8 nm, current reductions of ;20 over that for SiO2 films have been obtained for gate voltages in the range 1-1.5 V. For comparison, the thickness of the oxynitrides was obtained by X-ray photoelectron spectroscopy of the Si 2p, N 1s, and O 1s photoelectrons. By analyzing the yield from thick silicon dioxide and silicon nitride films, the electron escape depth in silicon nitride was estimated to be 1.7 nm for the Si 2p electrons. By correcting the measurements of the oxygen/nitrogen concentration ratio obtained from the O 1s and N 1s XPS peaks, and calculating the dielectric constant with a Bruggeman effective medium approximation, the equivalent oxide thickness was calculated. Agreement to ;0.2 nm was obtained with t eq determined by the CV analysis. Information obtained from the XPS analysis can also give information about bonding configurations and possible errors due to nonuniform stoichiometry as a function of depth.

Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress

This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in Gm decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior.

Resistive Switching Mechanism of Oxygen-Rich Indium Tin Oxide Resistance Random Access Memory

This letter investigates the double-ended resistive switching characteristics of indium tin oxide (ITO) resistance random access memory (RRAM). Resistive switching can be achieved around both the active TiN electrode and the inert Pt electrode. In addition, complementary resistance switching (CRS) characteristics can be observed without current compliance during dc voltage sweep operations. Electrical measurement data fitting results indicate that the oxygen-rich ITO near top and bottom electrodes works as a double-ended resistive switching layer. Based on the analysis of the current conduction mechanism, we propose a physical model to interpret the CRS behaviors in ITO RRAM devices.

Investigation of an anomalous hump in gate current after negative-bias temperature- instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors

This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ehigh-k = Q + Esio2esio2.

On the Origin of Anomalous Off–Current Under Hot Carrier Stress in p-Channel DDDMOS Transistors With STI Structure

This letter investigates the abnormal off-current behavior induced by hot carrier stress (HCS) in p-channel double diffused drain metal-oxide-semiconductor transistors with a shallow trench isolation (STI) structure. According to ISE-TCAD simulation, the electric field at the drain-side corners of the high-voltage n-well (HVNW) adjacent to the STI trench is stronger than the electric field in the channel center in width direction. Moreover, because a nitride layer acts as a buffer in STI, the electrons generated by impact ionization at the corners of the HVNW can be easily trapped in the nitride layer or at the liner oxide/nitride layer interface. Furthermore, the extension of electron trapping in STI from drain to source during HCS forms the off-current conductive path. Based on the charge pumping measurements at different operation conditions, this path formation is further demonstrated by the comparisons of charge pumping measurements between initial state and after HCS.

Influence of an anomalous dimension effect on thermal instability in amorphous- InGaZnO thin-film transistors

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast ID-VG and modulated peak/base pulse time ID-VD measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

High-k shallow traps observed by charge pumping with varying discharging times

In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks. NT-Vhigh level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of NT for extra contribution of Icp traps. NT is the number of traps, and Icp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of Icp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different TixN1−x metal gate concentrations. Next, NT-Vhigh level characteristic curves with different falling times (tfalling time) and base level times (tbase level) show that extra contribution of Icp traps decrease with an increase in tfalling time. By fitting discharge formula for different tfal...