Osbert Cheng

Comparison of the trap behavior between ZrO 2 and HfO 2 gate stack nMOSFETs by 1/f noise and random telegraph noise

Low-frequency (1/<i>f</i>) noise characteristics of 28-nm nMOSFETs with ZrO₂/SiO₂ and HfO₂/SiO₂ dielectric gate stacks have been investigated. The observed lower 1/<i>f</i> noise level in ZrO₂ devices, as compared with that in HfO₂ devices, is attributed to the reduction in tunneling attenuation length and in trap density simultaneously. Experimental results showed that the trap behavior of ZrO₂/SiO₂ dielectric gate stack changes not only the trap location from a high-<i>k</i> layer to a SiO₂ interfacial layer but also the noise-dominated mechanism from carrier number fluctuation to the unified fluctuation model, which includes number fluctuation and correlated mobility fluctuation.

Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors

This paper investigates the channel hot carrier stress (CHCS) effects on gate-induced drain leakage (GIDL) current in high-k/metal-gate n-type metal-oxide-semiconductor field effect transistors. It was found that the behavior of GIDL current during CHCS is dependent upon the interfacial layer (IL) oxide thickness of high-k/metal-gate stacks. For a thinner IL, the GIDL current gradually decreases during CHCS, a result contrary to that found in a device with thicker IL. Based on the variation of GIDL current at different stress conditions, the trap-assisted band-to-band hole injection model is proposed to explain the different behavior of GIDL current for different IL thicknesses.

On the Origin of Hole Valence Band Injection on GIFBE in PD SOI n-MOSFETs

This letter systematically investigates the mechanism of gate-induced floating-body effect (GIFBE) in advanced partially depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Based on different operation conditions, we found that the hole current collected by the body terminal is strongly dependent on electrons in the inversion layer under a source/drain ground. This implies that GIFBE can be attributed to anode hole injection (AHI) rather than the widely accepted mechanism of electron valence band tunneling. Moreover, GIFBE was also analyzed as a function of temperature. The results provide further evidence that the accumulation of holes in the body results from the AHI-induced direct tunneling current from the gate.

On the Origin of Gate-Induced Floating-Body Effect in PD SOI p-MOSFETs

This letter systematically investigates the origin of gate-induced floating-body effect (GIFBE) in partially depleted silicon-on-insulator p-type MOSFETs. The experimental results indicate that GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of negative-bias temperature instability degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n+ polygate. However, based on different operation conditions, we found that the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. This suggests that the mechanism of GIFBE at higher voltages is dominated by the proposed anode electron injection model, rather than the electron valence band tunneling widely accepted as the mechanism for n-MOSFETs.

Impact of Mechanical Strain on GIFBE in PD SOI p-MOSFETs as Indicated From NBTI Degradation

This letter investigates the impact of mechanical strain on gate-induced floating-body effect in partially depleted silicon-on-insulator p-channel metal-oxide-semiconductor field-effect transistors. The strained FB device has less NBTI degradation than unstrained devices. This behavior can be attributed to the fact that more electron accumulation induced by strain effect reduces the electric oxide field significantly during NBTI stress. Analysis of the body current under source/drain grounded and floating operation indicates an increase in the anode electron injection and electron tunneling from conduction band which occur at the partial poly-Si gate and Si substrate, respectively. This phenomenon can be attributed to the bandgap narrowing which has been induced by the strain effect.

Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors

The use of low-frequency (1/f) noise to evaluate stress-memorization technique (SMT) induced-stress in n-channel metal-oxide-semiconductor field-effect transistors is investigated. Through observing Hooge’s parameter αH, we found that the unified model can properly interpret the 1/f noise mechanism in our device. On the other hand, lower normalized input-referred noise (LSVG) level in number-fluctuation-dominated regime (region I) and smaller curvature of LSVG versus VGS-VTH in mobility-fluctuation-dominated regime (region II) are attributed to the reduced tunneling attenuation length and Coulomb scattering coefficient, respectively. It represents an intrinsic benefit of 1/f noise behavior stemming from SMT-induced more strain in short channel device.

Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress

This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in Gm decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior.

Impact of oxygen annealing on high-k gate stack defects characterized by random telegraph noise

The impact of post metal-deposition annealing (PMA) on the trap behavior of high-k/metal-gate metal-oxide-semiconductor field-effect transistors has been studied using drain current random telegraph noise (RTN). The RTN phenomenon is influenced by both trap positions and trap energy, thus corresponding with the PMA passivation mechanism. We found that trap positions in mono-metal-layer annealed (TiN annealed) devices are closer to the TiN/HfO2 interface due to the substitution of nitrogen atoms by oxygen atoms inside the TiN layer. However, replaced nitrogen atoms from TaN can passivate nitrogen defects in TiN that improves device characteristics in dual-metal-layer annealed (TiN/TaN annealed) devices.

Correlation Between Random Telegraph Noise and

The random telegraph noise (RTN) characteristics of 28-nm pMOSFETs with tip-shaped SiGe source/drain have been investigated. RTN analysis found that strained devices undergo higher compressive strain; the trap position from the Si/SiO2 interface is reduced, because of the closer trap energy level near the valence band. Although tip-shaped SiGe process induces higher oxide trap density, the trap position corresponding to the tunneling attenuation length (λ) may result in lower 1/f noise level in tip-shaped SiGe S/D devices as compared with that of control devices.

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This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k ehigh-k = Q + Esio2esio2.