Hua-Min Li

Ultimate thin vertical p–n junction composed of two-dimensional layered molybdenum disulfide

Semiconducting two-dimensional crystals are currently receiving significant attention because of their great potential to be an ultrathin body for efficient electrostatic modulation, which enables to overcome the limitations of silicon technology. Here we report that, as a key building block for two-dimensional semiconductor devices, vertical p–n junctions are fabricated in ultrathin MoS2 by introducing AuCl3 and benzyl viologen dopants. Unlike usual unipolar MoS2, the MoS2 p–n junctions show ambipolar carrier transport, current rectification via modulation of potential barrier in films thicker than 8 nm and reversed current rectification via tunnelling in films thinner than 8 nm. The ultimate thinness of the vertical p–n homogeneous junctions in MoS2 is experimentally found to be 3 nm, and the chemical doping depth is found to be 1.5 nm. The ultrathin MoS2 p–n junctions present a significant potential of the two-dimensional crystals for flexible, transparent, high-efficiency electronic and optoelectronic applications.

Metal-Semiconductor Barrier Modulation for High Photoresponse in Transition Metal Dichalcogenide Field Effect Transistors

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

Modulation of Quantum Tunneling via a Vertical Two-Dimensional Black Phosphorus and Molybdenum Disulfide p–n Junction

Diverse diode characteristics were observed in two-dimensional (2D) black phosphorus (BP) and molybdenum disulfide (MoS2) heterojunctions. The characteristics of a backward rectifying diode, a Zener diode, and a forward rectifying diode were obtained from the heterojunction through thickness modulation of the BP flake or back gate modulation. Moreover, a tunnel diode with a precursor to negative differential resistance can be realized by applying dual gating with a solid polymer electrolyte layer as a top gate dielectric material. Interestingly, a steep subthreshold swing of 55 mV/dec was achieved in a top-gated 2D BP-MoS2 junction. Our simple device architecture and chemical doping-free processing guaranteed the device quality. This work helps us understand the fundamentals of tunneling in 2D semiconductor heterostructures and shows great potential in future applications in integrated low-power circuits.

Enhancement of light absorption using high-k dielectric in localized surface plasmon resonance for silicon-based thin film solar cells

The application of high-dielectric-constant (k) materials, e.g., Si3N4, ZrO2, and HfO2, to localized surface plasmon resonance (LSPR) excited by a Au nanoparticle structure has been investigated and simulated for the enhancement of light absorption in Si-based thin film solar cells by using Mie theory and three-dimensional finite-difference time-domain computational simulations. As compared to a conventional SiO2 dielectric spacing layer, the high-k dielectrics have significant advantages, such as (i) a polarizability over two times higher, (ii) an extinction cross-section 4.1 times larger, (iii) a 5.6% higher transmission coefficient, (iv) a maximal 39.9% and average 25.0% increase in the transmission of the electromagnetic field, (v) an absorption of the transmitted electromagnetic field that is a maximum of 2.8 times and an average of 1.4 times greater, and (vi) increased absorption efficiency and extended cover range. Experimental results show that the average absorptance in the visible spectrum using...

Modified Potential Well Formed by

This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO₂/SiO_x,Na-TiO_x,N_y tunnel barrier, a trap-rich TiO₂ trapping layer, and an abrupt SiO₂ block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N₂ + O₂ thermal treatment, and the TiO₂ trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming (<; μs) at low-voltage operation (7-10 MV/cm), good P/E endurance (> 10⁶ P/E cycles), large threshold voltage window (ΔV_th =M> V), as well as improved data retention at 125 °C.

\hbox{Si/SiO}_{2}/ \hbox{TiN/TiO}_{2}/\hbox{SiO}_{2}/\hbox{TaN}

Various carbon based nanostructures (graphene, graphene-CNTs hybrid and three-dimensional (3D) carbon network) have been grown separately on low-temperature (600 ?C) substrates by using a chemical vapor deposition system with a two-heating reactor. The two-heating reactor is utilized to offer sufficient, well-proportioned floating C atoms and provide a simple method for low-temperature deposition. Morphology and electrical properties of the carbon based nanostructures can be controlled by the substrate surfaces. A relatively flat surface is beneficial for the synthesis of graphene and surfaces with nanodots are required to directly grow graphene-carbon nanotube hybrids. A chemical vapor deposition mechanism dependent on the temperature gradient is proposed, suggesting that the transfer-free carbon nanostructures can be deposited on different substrates. These results open an easy way for direct and high-efficiency deposition of various carbon nanostructures on the low-temperature dielectric substrates.

for Flash Memory Application

Potential well engineering is proposed for NAND Flash memory. With a variable (∼2nm–4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EWalso improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation. The EW demonstrated in this work is formed by partial oxidation of TiN at the interfaces of the SiO2/TiN/SiO2 stack during rapid thermal process (RTP), and its band profile is characterized by XPS, TEM, internal photoemission (IPE), XRD, and band simulation. The memory devices with an EW show promising performances in fast program (≪µs), low-voltage operation (6–8MV/cm), good 10-year data retention at 125°C, and excellent endurance (≫107 P/E cycles).

Low-temperature facile synthesis of graphene and graphene-carbon nanotubes hybrid on dielectric surfaces

An ultrahigh photocurrent (PC) signal which was about thousand times higher compared to the corresponding dark current was achieved in a two-dimensional (2D) multi-layer MoS2 field effect transistor (FET), owing to a gate-controlled MoS2/Ti/Au Schottky barrier (SB) modulation. The SBs can be enlarged for suppressing the electron drift along the channel in dark environment, and be reduced for the collection of photo-excited charge carriers in illuminating environment, providing the great potential for 2D electronic and optoelectronic applications.

Potential well engineering by partial oxidation of TiN for high-speed and low-voltage Flash memory with good 125°C data retention and excellent endurance

A drastic improvement in conversion efficiency was achieved from Si solar cells with radial-junction nanohole structure of a high aspect ratio of ∼10 which is fabricated by self-assembling plasma etching. A conversion efficiency of 27.8 % was predicted based on an optimization of various structural parameters by numerical simulations, and a design principle for realizing high efficiency Si nanohole surface texture for photovoltaic devices was demonstrated.

Gate-controlled Schottky barrier modulation for superior photoresponse of MoS 2 field effect transistor

This paper proposes a model established using the parallel connection of MOS and floating-gate MOS capacitors to examine the electric properties of polysilicon-oxide-nitride-oxide-silicon (SONOS) Flash memory in both the fresh and programmed states. A linear relationship between threshold voltage shift and effective trapped charge density was revealed via the threshold electric field. The simulation of the channel current was given based on our model, being in agreement with the experimental results for both forward and reverse read modes. The model and theory make an easy and time-saving approach to comprehensively analyze the trapped charge and its effect on other electric properties, e.g., electric field, oxide capacitance, and charge distribution, contributing to the control of the write/erase operation, the optimization of the device structure, and the characteristics of the retention properties in SONOS Flash memory.