Huan-Just Lin

Low power device technology with SiGe channel, HfSiON, and poly-Si gate

We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.

Reliability of HfSiON as gate dielectric for advanced CMOS technology

Optimizing nitrogen incorporation in HfSiON gate dielectric can improve overall reliability, e.g. nMOS PBTI lifetime, hot carrier (HC) lifetime, time-to-breakdown (tBD), without adverse effects on pMOS NBT1 lifetime and electron/hole mobility. The improvement is attributed to excellent thermal stability against partial-crystallization after 1100/spl deg/C annealing, and the concomitantly reduced trap generation minimizes stress induced leakage current (SILC) and flicker noise degradation after PBTI stress. A new methodology is proposed, for the first time, to correctly predict HC lifetime of HfSiON nMOS based on electron trapping.

Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond

Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines

We show that the mechanism of stress voiding in Cu/low-k vias is independent of width in the range 0.07 - 0.42 squarem. The resistance change associated with voiding shows saturation with stress time, implying that stress voiding is not a fundamental concern for continued feature size scaling. Stress voiding at narrow w is very sensitive to interconnect processing, and can give unexpected, large resistance increases with annealing.

III-V devices featuring Si transistor-like process and its heterogeneous integration on Si substrate

High mobility III-V compound semiconductors are the most attractive candidates who could provide enhanced performance for future logic applications. Even so, people still hesitate to accelerate III-V materials entering into Si CMOS world. To relieve peoples concerns, the integration of thin III-V on Si and Si transistor-like technique or architecture should be demonstrated.

HfSiON Gate Dielectric for 45nm Node Low-Power Device

A 1.4 nm EOT stack film of HfSiON with interfacial oxide layer (IL) is demonstrated with excellent electrical characteristics and reliability for 45 nm node low-power technology. Mobility comparable to SiON is achieved along with adequate nMOS PBTI lifetime, TDDB lifetime, and breakdown voltage (VBD). For the first time, we report lower VBD for the HfSiON stack film despite of 3 orders gate leakage reduction compared to the same EOT SiON. It is attributed to IL breakdown in the proposed two-step breakdown mechanism. This possibly limits the scalability of such a stack film. On the other side, over-drivability of HfSiON with thick underlying oxide boosts input/output (I/O) device performance significantly