Hui-Cheng Chang

Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate

A low interface trap density (Dit) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance–voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interface trap density Dit close to 5.5 × 1011 cm−2 eV−1. The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future.

Channel Stress Modulation and Pattern Loading Effect Minimization of Milli-Second Super Anneal for Sub-65nm High Performance SiGe CMOS

In this paper, we present an advanced integration approach using milli-second anneal technique to enhance device performance. In addition to enhanced poly-silicon activation, the device gain resulted from channel stress modulation, and retarded dopant diffusion can be obtained through process optimization including rapid-thermal anneal (RTA), capping layer, and milli-second anneal. More than 15% NMOS performance gain is demonstrated without undergoing milli-second-anneal-induced pattern loading effect and re-crystallization defect. No obvious stress relaxation and driving current degradation are observed in epi-SiGe PMOS. Moreover, the performance gain is increased while lowering the RTA temperature, suggesting that our proposed approach may open an alternative pathway for 45nm technology node and beyond

In 0.53 Ga 0.47 As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

In_0.53Ga_0.47As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In_0.53Ga_0.47As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS~95 mV/dec., I_on/I_off ~10⁵, DIBL ~51 mV/V at V_ds = 0.5V for L_g=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high field effect mobility (μ_EF = 1837 cm²/V-s with EOT ~ 0.9 nm) is among the highest values reported for surface channel In_0.53Ga_0.47As MOSFETs.

Investigation of Characteristics of Al2O3/n-In x Ga1−x As (x = 0.53, 0.7, and 1) Metal–Oxide–Semiconductor Structures

The electrical properties of Al2O3/n-InGaAs metal–oxide–semiconductor capacitors (MOSCAPs) with In content of 0.53, 0.7, and 1 (InAs) have been investigated. Results show small capacitance–voltage (C–V) frequency dispersion in accumulation (1.70% to 1.85% per decade) for these MOSCAPs, mostly being assigned to border traps in Al2O3. With higher In content, shorter minority-carrier response time and smaller C–V hysteresis are observed. The reduction of C–V hysteresis might be related to the reduction of Ga-bearing oxides in Al2O3/InGaAs interfaces as indicated by x-ray photoelectron spectroscopy.

Modeling and Characterization of Advanced Phosphorus Ultra Shallow Junction Using Germanium and Carbon Coimplants

A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.

Demonstration of a sub-0.03 um 2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of <;45mV/V and sub-threshold swing of <;65mV/decade and competitive drive current. Static noise margin of ~90mV for the high density SRAM operated down to 0.45V is achieved.