Hun-Jan Tao

25 nm CMOS Omega FETs

Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 /spl mu/A//spl mu/m and 780 /spl mu/A//spl mu/m with off state leakage currents of 8 nA//spl mu/m and 0.4 nA//spl mu/m for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 /spl mu/A//spl mu/m for N-FET and 550 /spl mu/A//spl mu/m for P-FET at an off current of 1 /spl mu/A//spl mu/m. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections.

Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphorization implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and S/D activation procedures. The stress modulation effect was found to be enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation. Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional /spl sim/10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process. which is a promising local strain approach for sub-65nm CMOS application.

35 nm CMOS FinFETs

We demonstrate for the first time high performance 35 nm CMOS FinFETs. Symmetrical NFET and PFET off-state leakage is realized with a simple technology. For 1 volt operation at a conservative 24 /spl Aring/ gate oxide thickness, the transistors give drive currents of 1240 /spl mu/A//spl mu/m for NFET and 500 /spl mu/A//spl mu/m for PFET at an off current of 200 nA//spl mu/m. Excellent hot carrier immunity is achieved. Device performance parameters exceed ITRS projections.

65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

High performance tantalum carbide metal gate stacks for nMOSFET application

A systematic study is performed on tantalum carbide (TaC) metal electrode on HfO2 and HfSiON dielectrics using conventional CMOS process. TaCs effective work function (EWF) is estimated to be 4.28 eV on HfO2 using Vfb~EOT methodology, where both interfacial oxide and high-K film thickness are varied and thus charge effect is corrected successfully. Investigation of the EWF dependence on underlying dielectrics reveals that TaC EWF on HfSiON is about 0.17eV higher than that on HfO2. This phenomenon cannot be explained by the usual metal induced gap states (MIGS) theory. In addition, mobility higher than 90% of poly/SiO2 reference and EOT scaling down to 12.5A has been achieved. Reduction of HfO2 thickness is identified as an effective approach to suppress charge trapping in the gate stack. With reduced thickness, threshold voltage stability and electron mobility are significantly improved. All these results prove that TaC/high-K stack is a promising candidate in nMOSFET application

Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide

A new circuit model of five elements has been proposed for the two-frequency capacitance-voltage (C-V) correction of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency C-V and static current-voltage (I-V) measurements if some criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate leakage current.

Low power device technology with SiGe channel, HfSiON, and poly-Si gate

We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

Reliability of HfSiON as gate dielectric for advanced CMOS technology

Optimizing nitrogen incorporation in HfSiON gate dielectric can improve overall reliability, e.g. nMOS PBTI lifetime, hot carrier (HC) lifetime, time-to-breakdown (tBD), without adverse effects on pMOS NBT1 lifetime and electron/hole mobility. The improvement is attributed to excellent thermal stability against partial-crystallization after 1100/spl deg/C annealing, and the concomitantly reduced trap generation minimizes stress induced leakage current (SILC) and flicker noise degradation after PBTI stress. A new methodology is proposed, for the first time, to correctly predict HC lifetime of HfSiON nMOS based on electron trapping.

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer

Transient charging and discharging of border traps in the dual-layer HfO2/SiO2 high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO2 high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10-8- 10-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling