Huan-Shun Huang

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

A 0.33-V, 500-kHz, 3.94-

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 × 385 μm2 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 °C. The measured total power consumption is 3.94 μW at 0.33 V, 500 kHz, and 25 °C .

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We present a 55nm 128Kb 6T SRAM with a variation-tolerant dual-tracking Word-Line Under-Drive (WLUD) to improve the RSNM and a Data-Aware Write-Assist (DAWA) scheme. Error free full functionality without redundancy is achieved from 1.5V down to 0.55V with area overhead of 4% for WLUD and 14% for DAWA, respectively. The measured power overheads (FF, 25oC) are 1.1% for WLUD and 3.3% for DAWA at 1.0V (3% and 5.3% at 0.6V), respectively. The maximum operating frequency is 940MHz (360MHz) at 1.0V (0.6V) and 25oC. The measured power/performance (FF, 25oC) is 0.117mW/MHz (0.023mW/MHz) at 1.0V (0.6V).

40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of areaefficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for VDD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 °C. At 0.325 V and 25 °C, the chip operates at 600 kHz with 5.78 μW total power and 4.69 μW leakage power, offering 2× frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 °C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

We present a theoretical study of the spin-dependent scattering of electrons from screened attractive and repulsive impurities in III-V semiconductor quantum wells. The effective one-band Hamiltonian and the Rashba spin–orbit interaction are used. We demonstrated that the asymmetry of the spin-dependent skew-scattering and side-jump effect can lead to a quite large spin-dependent (anomalous) Hall effect at zero magnetic field in all-semiconductor quantum well structures. Our theory predicts a measurable spin-dependent Hall angle that reaches about 2.5×10−3 rad for a CdTe/InSb/CdTe quantum well with impurities doped in the center of the well.We present a theoretical study of the spin-dependent scattering of electrons from screened attractive and repulsive impurities in III-V semiconductor quantum wells. The effective one-band Hamiltonian and the Rashba spin–orbit interaction are used. We demonstrated that the asymmetry of the spin-dependent skew-scattering and side-jump effect can lead to a quite large spin-dependent (anomalous) Hall effect at zero magnetic field in all-semiconductor quantum well structures. Our theory predicts a measurable spin-dependent Hall angle that reaches about 2.5×10−3 rad for a CdTe/InSb/CdTe quantum well with impurities doped in the center of the well.

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

This paper presents a 256kb 6T static random access memory (SRAM) with threshold power-gating (TPG), low-swing global read bit-line (GRBL), and charge-sharing write with Vtrip (VTP) tracking and negative source-line (NVSL) write-assists (WA). The TPG facilitates lower NAP mode voltage/power and faster wake-up for the cell array, while low-swing GRBL reduces the dynamic read power. A variation-tolerant charge-sharing write scheme, where the floating “Low” global write bit-line (GWBL) is used to capacitively couple down the local bit-line (LBL), is combined with a cell Vtrip-tracking and NVSL write-assists to improve the write-ability. The 256kb test chip is implemented in UMC 40nm low-power (LP) CMOS technology. Error-free full-functionality is achieved from 1.18GHz at 1.5V to 100MHz at 0.65V without redundancy. The TPG scheme reduces the power by 70% (55%) at 1.5V (0.5V) in NAP mode. The low-swing GRBL reduces dynamic read power by 3.5% (8%) at 1.1V (0.65V). The VTP-WA and NVSL-WA improve the write VMIN by 50mV (from 0.7V to 0.65V) and reduce write bit failure rate by 2.75× at 0.65V.

Spin-dependent Hall effect in semiconductor quantum wells

This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive Data-Aware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25°C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25°C.

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Abstract We present a theoretical study of the spin-dependent electron scattering from screened impurities in III–V semiconductor quantum wells. The effective one band Hamiltonian and the Rashba spin-orbit interaction are used. We calculated the Mott scattering cross-section and the Sherman function for two-dimensional electrons spin-polarized parallel to the z -axis (direction of structure growth). We have found a large spin-dependent asymmetry in the elastic cross-section for electrons scattered from impurities in CdTe/InSb/CdTe symmetrical semiconductor quantum wells. The Sherman function amplitude for repulsive impurities in CdTe/InSb/CdTe quantum wells is predicted to be about 0.01