Wei Hwang

A 500-MHz, 32-word/spl times/64-bit, eight-port self-resetting CMOS register file

A two-write-port, six-read-port, 32/spl times/64-bit register file has been designed for 2.5-V 0.5-/spl mu/m CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84/spl times/1.55 mm/sup 2/, and the cell size is 21.6/spl times/30 /spl mu/m/sup 2/. The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs.

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

This paper presents a fast, low-power, binary carry-lookahead, 64-bit dynamic parallel adder architecture for high-frequency microprocessors. The adder core is composed of evaluate circuits and feedback reset chains implemented by self-resetting CMOS (SRCMOS) circuits with enhanced testability. A new tool, SRCMOS pulse analyzer (SPA), is developed for checking dynamic circuits for proper operation and performance. The nominal propagation delay and power dissipation of the adder were measured to be 1.5 ns (at 22/spl deg/C with V/sub dd/=2.5 V) and 300 mW. The adder core size is 1.6/spl times/0.275 mm/sup 2/. The process technology used was the 0.5 /spl mu/m IBM CMOS5X technology with 0.25 /spl mu/m effective channel length and five layers of metal. The circuit techniques are easily migratable to multigigahertz microprocessor designs.

A pulse-to-static conversion latch with a self-timed control circuit

The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with SRCMOS test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance. An experimental 64-bit latch array and self-timed control macro, designed for 2.5 V-0.5 /spl mu/m CMOS technology, has been successfully fabricated and tested. The full circuit occupies an area of 1.704 mm/spl times/0.07 mm, and the size of latch bit cell is 21.6 /spl mu/m/spl times/70 /spl mu/m. Experimental results have shown the conversion latch to function properly, capturing 1.2 ns output pulses from an SRCMOS register file, and properly converting them to static levels. The measured delay from global clock to static output was 725 ps.

Design of provably correct storage arrays

In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register transfer level (RTL) specification with a low-level transistor implementation. Equivalence checking is increasingly applied in practical design flows to verify regular logic components. However, because of their specific organization and circuit techniques, high-performance implementations of large storage arrays require particular modifications to the general flow that make them suitable for formal equivalence checking. Two techniques are outlined in this paper. First, a special hierarchical verification scheme is described that allows the application of a partitioned comparison approach of the bit-wise organized transistor-level model with the word-wise organized RTL model. Second, a modified switch-level extraction technique is presented that extends the applicability of equivalence checking from regular dynamic CMOS circuits to self-resetting CMOS (SRCMOS) circuits.

Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

This paper presents mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuits for low-power, high performance and deep-submicron VLSI design. These logic circuits incorporate two different sets of CMOS devices, low-V/sub t/ and regular high-V/sub t/ CMOS devices. By appropriately selecting the low-V/sub t/ and high-V/sub t/ devices and configurations in a circuit, we can gain performance of circuit while keeping the leakage current and power low. The key approaches are using low-V/sub t/ devices to gain performance, using high-V/sub t/ devices to cut off the leakage path and also using the reverse-biased low-V/sub t/ devices in their standby state. The methodology and algorithm are developed and simulated. The applications of such multi-V/sub t/ circuit techniques to the static, domino NORA DCVS and delayed reset circuits are described. The use of footer/header devices, gated-Vdd and a mixture of low-V/sub t/ and high-V/sub t/ devices to reduce power dissipation and subthreshold leakage current during standby and active modes, and the global design issues are also discussed.

Development of a high bandwidth merged logic/DRAM multimedia chip

This paper describes the design methodology and the implementation of a merged logic/DRAM multimedia chip. The design is based on 0.25 micron DRAM-based CMOS technology with 4-layers of metal with device performance enhancement. Details of the architecture and system design of the multi-media was described in Katayama et. al. (1996). The present chip consists of 64 Mb of synchronous DRAM which is organized in two banks of eight 8 Mb SDRAM macros, a gate-array memory control and bus control unit, a custom-designed 8/spl times/32-bit parallel graphic processor, a 64-bit parallel ports for data transfer to/from the host processor bus, a 32-bit serial port for video display, and on-chip PLL. The multi-media co-processor chip provides high-density unified memory, high bus bandwidth (4.3 GB/s peak) and 1+GB/s BITBLT processing functions for an external host processor. The current design, floorplan and layout are structured in a way that, we believe, will provide a general framework for other merged logic/DRAM, ASIC+DRAM design for system scale integration.

A comparison of dual-rail pass transistor logic families in 1.5V, 0.18μm CMOS technology for low power applications

In this paper the results of an experimental comparison of popular pass-transistor logic families in 1.5V, 0.18µm CMOS technology using advanced CAD tools for circuit tuning and simulation are presented. The logic families were compared using an experimental setup designed to clarify the strengths and weaknesses of each family in a relative fashion and evaluate their individual performances under identical operating conditions. An automatic circuit tuner was used to help ensure that the test circuits from each logic family were operating at near optimum performance. It is shown that the Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic family is the most robust with respect to an amalgamation of speed, power, area and physical design criteria. The methodology of using hybrid pass-transistor / static CMOS circuit styles is also presented.

Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

This paper presents a fast, low power, binary carry look-ahead 64-bit dynamic parallel adder architecture for a high frequency microprocessor. The adder core is composed of several basic building blocks and feedback reset chain blocks implemented in self-resetting CMOS (SRCMOS) circuits. All circuits are design with enhanced testability. A new tool, SPA (SRCMOS Pulse Analyzer) is developed for dynamic and static checks. The nominal propagation delay and power dissipation of the adder are measured to be 1.5 ns (at 22 C with Vdd=2.5 V) and 300 mW. The adder core size is 1.6 mm/spl times/0.275 mm. The process that the design is based upon in a 0.5 /spl mu/m IBM CMOS5X technology with 0.25 /spl mu/m effective channel length and 5 layers of metal. The circuit techniques are ready to be migrated to sub-nanosecond microprocessor design.

Cool low power 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology (poster session)

This paper describes power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines x 64 bitlines) fabricated in 0.25 μm Silicon on Insulator (SOI) and bulk technologies. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.5% per 10§ C reduction in temperature. The standby power for SOI reduces by 1.5% to 3 per 10§ C temperature drop down to -30§ C. The SOI chip is shown to have more significant performance improvement at low temperatures compared to bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The low temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At 30§ C the register file is capable of functioning close to 1.02 GHz for read and write operations in a single cycle.

A 660 MHz self-resetting 8 port, 32/spl times/64 bits register file and latch in 0.25 /spl mu/m SOI technology

Design issues associated with dynamic circuits such as collisions, pulse widening, and noise margins are anticipated to be very sensitive to SOI process and device conditions. Multi-port dynamic register files and latches are important elements in current microprocessors. We designed such a register file and latch for bulk silicon technology, but it can be fabricated in SOI technology without any body contacts. The register file and latch function at frequencies higher than 660 MHz. The salient features are low voltage operability, fully collision-free operation and minimum noise. A robust design is demonstrated with respect to input pulse width variation and skew margins. Charge sharing noise and noise due to leakage coupling and power supply variations are controlled using half latches on the dynamic nodes and by properly optimizing circuits and layouts.