Huang-Chang Lee

An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding

This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. In order to provide sufficient memory bandwidth without the need for using registers, a FIFO-based check-mode memory, which dominates the decoder area, is used. Since two compensation factors, rather than a single factor, are dynamically used in the offset Min-Sum algorithm, the number of quantization bits, and, hence, the memory size, can be reduced without degradation in error performance. In order to further reduce the memory size, artificial minimum values, which do not need to be stored in memory, are used. We also propose an algorithm that can be used to partition variable nodes such that the hardware cost can be minimized. Using the proposed techniques, a multi-standard decoder that supports the LDPC codes specified in the ITU G.hn, IEEE 802.11n, and IEEE 802.16e standards was designed and implemented using a 90-nm CMOS process. This decoder supports 133 codes, occupies an area of 5.529 mm2 , and achieves an information throughput of 1.956 Gbps.

Two Informed Dynamic Scheduling Strategies for Iterative LDPC Decoders

When residual belief-propagation (RBP), which is a kind of informed dynamic scheduling (IDS), is applied to low-density parity-check (LDPC) codes, the convergence speed in error-rate performance can be significantly improved. However, the RBP decoders presented in previous literature suffer from poor convergence error-rate performance due to the two phenomena explored in this paper. The first is the greedy-group phenomenon, which results in a small part of the decoding graph occupying most of the decoding resources. By limiting the number of updates for each edge message in the decoding graph, the proposed Quota-based RBP (Q-RBP) schedule can reduce the probability of greedy groups forming. The other phenomenon is the silent-variable-nodes issue, which is a condition where some variable nodes have no chance of contributing their intrinsic messages to the decoding process. As a result, we propose the Silent-Variable-Node-Free RBP (SVNF-RBP) schedule, which can force all variable nodes to contribute their intrinsic messages to the decoding process equally. Both the Q-RBP and the SVNF-RBP provide appealing convergence speed and convergence error-rate performance compared to previous IDS decoders for both dedicated and punctured LDPC codes.

Channel estimation for OFDM system with two training symbols aided and polynomial fitting

A time-varying channel estimation method for orthogonal frequency division multiplexing (OFDM) systems is presented. The presented channel estimation method employs two training symbols in combination with polynomial fitting, thus obtaining accurate estimation results under a large normalized Doppler frequency.

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz , achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.

LDPC Decoding Scheduling for Faster Convergence and Lower Error Floor

This paper presents a maximum mutual information increase (M2I2)-based algorithm that can be used to arrange low-density parity-check (LDPC) decoding schedules for faster convergence, where the increase is used to guide the arrangement of the fixed decoding schedule. The predicted mutual information for the messages to be updated is used in the calculation of the increase. By looking ahead for several decoding stages, a high-order prediction can be realized, which can then be used to devise a schedule with an even faster convergence. For a single received frame, different decoding results can be obtained using different schedules, and, hence, schedule diversity, that lowers the error floor resultant from the dominant trapping sets, is proposed. By adopting the M2I2-based schedule together with the schedule diversity, both the convergence speed in the waterfall region and the error-rate in the floor region can be improved.

Less Complexity Successive Interference Cancellation for OFDM System

The Vertical Bell Laboratories Layered Space Time (V-BLAST) detection presented for multiple-input multiple- output (MIMO) system can also be used for orthogonal frequency division multiplexing (OFDM) signal detection, and is referred as the successive interference cancellation (SIC) method. In the paper a refined SIC algorithm is first presented. Then, several less complexity modified SIC algorithms for OFDM signal detection in multi-path fading channel are presented. The presented modified SIC algorithms can significantly reduce the computation complexity of SIC and meanwhile maintain excellent performance.

Flooding-assisted informed dynamic scheduling for rateless codes

As part of the tradeoff between error performance, decoding complexity and the overhead of rateless codes, the combination of incremental decoding (ID) and informed dynamic scheduling (IDS), known as IDIDS (incremental decoding with informed dynamic scheduling), is an attractive solution in binary symmetric channels (BSC). However, applying IDIDS in the AWGN (additive white Gaussian noise) channel may cause a degradation in BER performance, since the incrementally received symbols from the AWGN channel may not be immediately utilized in the decoding process directed by IDS. In addition, a stopping criterion combined with IDS may cause the current decoding attempt to terminate too early, and the channel information contained in the originally received codeword will not be used efficiently. In this paper, a dynamic decoding schedule strategy is proposed. In the proposed decoder, the new received symbols can be immediately utilized in the decoding process. For Luby transform (LT) codes and Raptor codes over the AWGN channel, the proposed algorithm provides a more balanced tradeoff. In the case of Raptor codes, the BER performance is obviously improved.

Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders

For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) messages is not needed and, hence, the memory area can be minimized, but at the cost of increased data dependency. This paper presents three techniques that can be used to implement an efficient reordered layered decoder. First, with the assistance of a graph coloring method, the required minimum number of V2C sign memory banks can be theoretically determined, with the corresponding pipeline architecture also designed. After that, the integer linear programming technique is adopted so as to arrange the V2C sign memory banks in a manner that minimizes the number of pipeline stalls, thereby increasing throughput. In order to further simplify the decoder, the first minimum values are not stored if the proposed modified min-sum algorithm is used. The proposed techniques are demonstrated by implementing a rate-0.905 (18396,16644) QC-LDPC decoder using 90-nm CMOS technology. When using the proposed techniques, implementation results show that the throughput-to-area ratio (TAR) increases by 58.9% without sacrificing error-rate performance.

A Construction of Physical-Layer Systematic Raptor Codes Based on Protographs

A construction of physical-layer Raptor (PLR) codes based on protographs is proposed. We first set up a sequence of signal-to-noise ratios (SNRs). For each SNR, we employ a modified protograph EXIT analysis to find the extra check nodes in addition to the existing check nodes so as to meet the threshold required by the outer low-density parity check code. PLR codes which are capacity-approaching for a wide SNR range can be obtained using the proposed construction.

Informed dynamic schedules for LDPC decoding using belief propagation

After the publication of the residual belief-propagation (RBP) algorithm, many low-density parity-check (LDPC) decoders using informed dynamic scheduling (IDS) have been investigated. In this paper, we propose the twofold-RBP (T-RBP) decoder that combines two residuals. Using T-RBP, significant improvement can be achieved in both convergence speed and convergence error-rate performance. In addition to T-RBP, the simplified-RBP (S-RBP) decoder is also proposed in order to reduce the complexity. Instead of comparing all the residuals of all edges in the code graph, as with previous IDS decoders, S-RBP only compares the residuals of the edges connected to a single check node, thus dramatically reduces the complexity without any significant degradation in performance. The proposed T-RBP and S-RBP can improve not only the performance of dedicated codes, but also that of punctured codes, especially the convergence speed. The improvement can make punctured LDPC codes more practical and becoming a competitive candidate for the rate compatible applications.