Huang-Yu Chen

Full-Chip Routing Considering Double-Via Insertion

As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times.

Novel full-chip gridless routing considering double-via insertion

As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the post-layout stage. The increasing design complexity, however, leaves very limited space for post-layout optimization. It is thus desirable to consider the double-via insertion at both routing and post-routing stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework. We also propose a new post-layout double-via insertion algorithm to achieve a higher insertion rate. Based on a bipartite graph matching formulation, we develop an optimal double-via insertion algorithm for the cases with up to three routing layers and the stack-via structure, and then extend the algorithm to handle the general cases. Experiments show that our methods significantly improve the via count, the number of dead vias, double-via insertion rates, and running times

Multi-layer global routing considering via and wire capacities

Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.

Novel wire density driven full-chip routing for CMP variation control

As nanometer technology advances, the post-CMP dielectric thickness variation control becomes crucial for manufacturing closure. To improve CMP quality, dummy feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and lead to explosion of mask data. It is thus desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider wire distribution, the router applies a novel two-pass, top-down planarity-driven routing framework, which employs a new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve more balanced wire distribution than state-of-the-art works.

A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control

As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following time-consuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.

Density gradient minimization with coupling-constrained dummy fill for CMP control

In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase interconnect coupling capacitance and thus circuit delay, and might also lead to explosion of mask data due to the extra layout patterns. Traditional dummy-fill algorithms try to make each tile (window) density satisfy foundrys density upper and lower bounds under the coupling constraint. As technology advances, however, it is not sufficient to just keep the pattern density variation of each layer within density bounds. The density gradient, besides the density variation, plays a pivotal role in determining the post-CMP thickness of modern circuit designs. In this paper, we present the first gradient-driven dummy-fill algorithm to address the density gradient and other classical objectives (such as density variation, coupling constraints, dummy count) as well. Our dummy-fill algorithm has the two distinguished features: (1) Gaussian smoothing based gradient-driven multilevel dummy density analysis to minimize density gradient level by level, and (2) ILP-based fill synthesis to insert the fewest dummies within the coupling-violation-free feasible regions while satisfying the density constraints. Experimental results show that our algorithm can achieve promising results by inserting minimal dummies to reduce the density gradient and variation under the coupling constraints with a reasonable runtime overhead.

Multilayer Global Routing With Via and Wire Capacity Considerations

Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing is presented. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage.

Global and detailed routing

Publisher Summary This chapter focuses on routing, a process that determines the precise paths for nets on the chip layout to interconnect the pins on the circuit blocks or pads at the chip boundary. These precise paths of nets must satisfy the design rules provided by chip foundries to ensure that the designs can be correctly manufactured. The chapter first formulates the global and detailed routing as graph-search problems and examines the general-purpose routing algorithm, which includes the maze, line-search, and A*-search routing, and can be applied to both global and detailed routing. The techniques of general-purpose routing are described followed by the introduction of popular global-routing algorithms that cover sequential and concurrent approaches. The most important objective of routing is to complete all the required connections; otherwise, the chip would not function well and may even fail. Other objectives, such as reducing the routing wire length and ensuring that each net satisfies its required timing budget, have become essential for modern chip design. The modern routing techniques considering signal integrity and chip manufacture and yield are reviewed. The chapter concludes with routing trends and future directions of routing. After reading through the chapter, the reader should have a clear picture about popular global and detailed routing algorithms. This background is valuable in implementing/developing routing algorithms to meet the design needs.

Routing for manufacturability and reliability

As IC process geometries scale down to the nanometer territory, industry faces severe challenges of manufacturing limitations. To guarantee high yield and reliability, routing for manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this article, we introduce major routing challenges arising from nanometer process, survey key existing techniques for handling the challenges, and provide some future research directions in routing for manufacturability and reliability.

Physical Design for System-On-A-Chip

This chapter is focused on the physical design for system-on-a-chip (SOC). Physical design refers to all synthesis steps that convert a circuit representation (gates, transistors) into a geometric representation (polygons and theirs shapes). See Figure 1 for an illustration. The geometric representation, also called layout , is used to design masks and then manufacture a chip. As a very complicated design process, modern physical design is typically divided into three major steps: floorplanning , placement , and routing. Floorplanning is an essential design step for hierarchical, building block design methodology. Given a set of hard blocks (whose shapes cannot be changed) and/or soft blocks (whose shapes can be adjusted) and a netlist, floorplanning determine the shapes of soft blocks and assemble the blocks into a rectangle (chip) such that a predefined cost metric (such as the chip area, wirelength, wire congestion) is optimized. Placement is the process of assigning the circuit components into a chip region. It can be considered as a restricted floorplanning problem for hard blocks with some dimension similarity. Following placement, the routing process defines the precise paths for conductors that carry electrical signals on the chip layout to interconnect all pins that are electrically equivalent. After routing, some physical verification processes (such as design rule checking (DRC), performance checking, and reliability checking) are performed to verify if all geometric patterns, circuit timing, and electrical effects satisfy the design rules and specifications.