Ru-Gun Liu

Two threshold resist models for optical proximity correction

There have been several kinds of resist model proposed for optical proximity correction. The simplest one is the constant threshold resist model. By this method, only area with intensity above a certain threshold value would be developed. Unfortunately, the constant threshold resist model is too simplified to accurately describe the entire resist processes. To solve this problem, variable threshold resist models were proposed thereafter. The printed resist edge is characterized in terms of the aerial image properties, such as intensity, intensity slope and so forth. More parameters and freedoms are required to describe the complicated chemical reactions of the resist during exposure and development processes. However, the computation time for OPC would increase significantly due to the supplementary calculation of the extra aerial image properties. In this paper, the dual model of constant threshold was proposed to enhance the accuracy of constant threshold resist models. Two constant threshold resist models were determined by model fitting process based on different types of pattern structures. During the correction, one-dimensional and two-dimensional edges are identified first and different constant-threshold models were applied for simulation. Good corrections on both of the one-dimensional line/space widths and two-dimensional line-ends could be achieved. The simulation results were also compared with experimental data.

Mask cost and cycle time reduction

In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRSs roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.

OPC modeling by genetic algorithm

Optical proximity correction (OPC) is usually used to pre-distort mask layouts to make the printed patterns as close to the desired shapes as possible. For model-based OPC, a lithographic model to predict critical dimensions after lithographic processing is needed. The model is usually obtained via a regression of parameters based on experimental data containing optical proximity effects. When the parameters involve a mix of the continuous (optical and resist models) and the discrete (kernel numbers) sets, the traditional numerical optimization method may have difficulty handling model fitting. In this study, an artificial-intelligent optimization method was used to regress the parameters of the lithographic models for OPC. The implemented phenomenological models were constant-threshold models that combine diffused aerial image models with loading effects. Optical kernels decomposed from Hopkin’s equation were used to calculate aerial images on the wafer. Similarly, the numbers of optical kernels were treated as regression parameters. This way, good regression results were obtained with different sets of optical proximity effect data.

Progress and outlook of lithography for semiconductor IC

Progress of lithography from the lensless type to lens-based systems using different kinds of photon and electron beams is reported here. The stages of lithography development with their physical principles are linked to the corresponding impacts to IC designers to help them understand the reasons they are more and more restricted. From this vantage point, we look at the prospects of the lithography systems that will handle patterning for 32-nm half pitch and beyond in feasibility and cost.

Mask error tensor and causality of mask error enhancement for low- k 1 imaging: theory and experiments

Three important concepts about the mask error enhancement factor (MEEF) are proposed. From the definition of MEEF, it could be derived as a function of the image log slope and the aerial image variation caused by mask critical dimension (CD) errors. Second, a mask error common window indicator (MECWIN) is proposed to evaluate the MEEF and mask CD specification by knowing the wafer CD tolerance. This concept is used to define the mask CD specification without any ambiguity. Finally, we describe the complex 2-D response to the mask-making error around the line end by a mask error enhancement tensor. Both theoretical derivations and experiments to justify the theory are presented.

Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application

Embedded FeRAM module is achieved by a low temperature capacitor-over-interconnect (COI) process. A conductive perovskite LaNiO/sub 3/ (LNO) bottom electrode is used as seed layer, the crystallization temperature of in-situ sputter deposited PZT is greatly reduced from 600/spl deg/C to 350 /spl deg/C/spl sim/400/spl deg/C LNOs near-perfect lattice match with PZT allows PZT to growth epitaxially at low temperature. When LNO is used as top electrode of the ferroelectric capacitor, the fatigue performance is greatly improved. The COI LNO/PZT/LNO FeRAM structure achieved by this low temperature process is completely modular and is ideal for advanced Cu/low-K SOC application.

Mask lithographic performance investigation with computational Monte-Carlo method on advanced mask patterning

As semiconductor features shrink in dimension and pitch, the excessive control of critical-dimension uniformity (CDU) and pattern fidelity is essential for mask manufacturing using electron-beam lithography. Requirements of the electronbeam shot quality affected by shot unsteadiness become more important than before for the advanced mask patterning. Imperfect electron optical system, an inaccurate beam deflector, and imprecise mask stage control are mainly related to the shot unsteadiness including positioning and dose perturbations. This work extensively investigates impacts of variable shaped beam dose and positioning perturbations on local CDU using Monte Carlo simulation for various mask contrast enhancement approaches. In addition, the relationship between the mask lithographic performance and the shot count number correlated with mask writing time is intensively studied.

Inverse polarizer on immersion lithography mask

The inverse polarizing effect of Sub-Wavelength Metallic Gratings (SWMGs) is employed to improve the lithography performance by controlling the polarization. The SWMGs are intentionally created on the top surface of mask. Its polarization selectivity is deliberately designed according to the bottom mask patterns. A series of simulations and optimizations on SWMG structures were done in order to achieve better image quality. We demonstrate that the contrast of aerial image can be improved by designing the inverse polarizer on mask (iPOM) for some specific layout patterns. We also reveal that the double diffraction inevitably occurring in-between the iPOM and layout pattern may damage the image quality in most situations. This leads to narrow usage of iPOM. An alternative to overcome the double diffraction is proposed by optimizing the refractive index and thickness of layout absorber to make the polarization selection feasible without iPOM.

Phenomena and OPC solution of ripple patterns for 65-nm node

The ripple patterns induced by the lithography process will lead to unpredictable necking or bridging risks on circuit patterns. This phenomenon is particularly severe while using the attenuated-phase-shifting mask combined with the strong off-axis illumination. The CD variation induced by the ripple effect is difficult to be accurately corrected by conventional OPC approaches. In this paper, ripples on patterning for the 65nm node have been studied and their problems solved. One of the dominant root causes of ripples is the optical side-lobes from the surrounding patterns. On the L-shape patterns for example, the ripples that occur on the horizontal lines are induced by the side-lobes of the vertical lines. Based on this study of the ripple effect, the layout types resulting in ripple patterns can be classified and predicted. An advanced OPC approach by the segmentation analysis on polygons as well as the correction algorithm optimization has been developed and applied to solve this ripple problem.

180nm Sn-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applications

A 180 nm phase-change device is developed for embedded SoC memory to replace both DRAM and Flash memories. In order to reduce power consumption, the total volume of the device must be reduced and the programming speed must be increased. The speed of programming and reading of chalcogenide memory devices is investigated. It is discovered that the writing speed of the devices using Ge/sub 2/Sb/sub 2/Te/sub 5/ as the storage media is compromised when the chalcogenide film is ultra thin. With doping of Sn, the writing speed is dramatically increased. The maximum programming time (SET) is reduced from 200 ns to 40 ns and that for RESET from 40 ns to 10 ns. Moreover, the reading speed is also improved as a result of lower resistance.