Huaxing Tang

Improved volume diagnosis throughput using dynamic design partitioning

A method based on dynamic design partition is presented to increase the throughput of volume diagnosis by increasing the number of failing dies diagnosed within a given time T using given constrained computational resources C. Recently we proposed a static design partitioning method to reduce the diagnosis memory footprint for large designs [1] to achieve this objective. The method in [1] is applied once for each design without using the information of test patterns and failure files, and then diagnosis is performed on an appropriate block(s) of the design partition for a failure file. Even though the memory footprint of diagnosis is reduced the diagnosis quality is impacted to unacceptable levels for some types of defects such as bridges. In this paper, we propose a new failure dependent design partitioning method to improve volume diagnosis throughput with a minimal impact on diagnosis quality. For each failure file, the proposed method first determines the small partition needed to diagnose this failure, and then performs the diagnosis on this partition instead of the complete design. Since the partition is far smaller, both the run time and the memory usage of diagnosis can be significantly reduced better than when earlier proposed static partition is used. Extensive experiments were conducted on several large industrial designs to validate the proposed method. It has been observed that the typical partition size for various defects is less than 3% of the size of the original design. Also diagnosis runs much faster (>;2X) on the partition. Combining these two factors, the throughput of volume diagnosis can be improved by an order of magnitude.

Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault Models

The industry is encountering an increasing number of front-end-of-line defects in the most advanced technology nodes due to extremely small feature size and complex manufacturing processes. Traditional scan diagnosis algorithms can locate a defective cell by examining its excitation conditions for cell internal defects, but cannot provide the more precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we propose a new cell-aware diagnosis algorithm, based on accurate fault models derived by analog simulation, that can pinpoint the defect location within a cell for various cell internal defects. The proposed method already has achieved dramatic resolution improvement for real silicon failures.

Distributed dynamic partitioning based diagnosis of scan chain

Diagnosis memory footprint for large designs is growing as design sizes grow such that the diagnosis throughput for given computational resources becomes a bottleneck in volume diagnosis. In this paper, we propose a scan chain diagnosis flow based on dynamic design partitioning and distributed diagnosis architecture that can improve the diagnosis throughput over one order of magnitude.

Diagnose Failures Caused by Multiple Locations at a Time

Fault diagnosis plays an important role in physical failure analysis and yield learning process. With tens of billions of transistors being integrated in one chip, multiple faults may exist. With multiple faults, fault masking and reinforcing effects may appear. They may cause the conventional single-fault-based diagnosis methods such as the single location at a time (SLAT) to be invalid. The popular SLAT approach fails if there are not enough SLAT patterns that can be explained by a single stuck-at fault. Moreover, a real silicon defect may behave as different fault models (DM) under different failing patterns, which may invalidate the SLAT approach that uses a single-fault model across all failing patterns. In this paper, we introduce the concept of fault element to support multiple fault models, and use a fault-element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. Based on the FEGs of all failing patterns, the most likely fault locations and their fault elements are iteratively identified. Meanwhile, the FEGs are iteratively pruned to keep track of the remaining multiple fault effects until all the fault locations are identified and all the FEGs are reduced to null. Experiments demonstrate that the proposed diagnosis method can identify the locations of multiple faults even under DM with high diagnostic accuracy and resolution.

Cell-aware diagnosis: Defective inmates exposed in their cells

Volume diagnosis of scan fails is au effective method of identifying dominant defect mechanisms for yield improvement. However, traditional diagnosis is at the library cell level and identifies only interconnect defects and defective cells. In practice, many defects affect only the internal logic of cells, such as polysilicon contacts, but cannot be pinpointed, resulting in not identifying some potential yield limiters. This paper describes a solution to the problem by showing how diagnosis can be extended to internal cell defects. This is enabled by characterizing a cell library similar to what is needed for cell-aware ATPG, but including more information for diagnosis such as layout data. A flow is described to produce the characterization, which includes requirements for the cell views. Diagnosis results include layout marker files for cell internal suspects which can be viewed in a GDS newer and used to obtain X/Y coordinates to guide physical failure analysis. Successful implementation is demonstrated for a 160nm automotive product.

Diagnosing timing related cell internal defects for FinFET technology

The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional delay diagnosis algorithm has a limited support for cell internal timing related failures based on transition delay faults, and tends to provide a large suspect list. It cannot provide the precise defect location inside the cell that is necessary for effective physical failure analysis and statistical yield learning. In this work, we present a new cell-aware delay diagnosis algorithm, based on accurate delay fault models derived by analog simulation, which can pinpoint the defect location within a cell for various timing related cell internal defects. Preliminary results for real silicon failures show that significant diagnosis resolution improvement can be achieved by the proposed method.