Wu-Tung Cheng

PROOFS: a fast, memory-efficient sequential circuit fault simulator

The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits, PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits. >

Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm

A stand-alone design automation tool tailored for radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) low-noise amplifier (LNA) designs is presented. Rather than relying on commercially available circuit simulators such as Spectre or Hspice, the presented synthesis tool is self-contained with its own built-in modules for faster optimization. Foundry-provided silicon-verified RF device models are incorporated into the synthesis procedure for accurate parasitic modeling. The proposed synthesis tool can be used as an independent circuit design environment for LNAs or, alternatively, as an auxiliary tool generating an initial design for a commercial design environment to reduce design time. To validate the proposed approach, an LNA operating at 900 MHz is synthesized and fabricated in a 0.25-mum CMOS technology. Measurement results are presented, which shows the viability of the proposed synthesis tool.This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

Statistical diagnosis for intermittent scan chain hold-time fault

Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed a s well. Unlike the previous scan chain diagnosis methods that targeted p ermanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location o f candidate faulty scan cells is obtained. Second a n ew method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of t he bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains.

Compactor independent direct diagnosis

In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression.

X-filter: filtering unknowns from compacted test responses

Using off-the-shelf error correcting codes for compacting test response (Patel, 2003) is attractive because it provides multiple error detection and diagnosis support in the presence of multiple unknowns. However, this technique is not easily incorporated in a conventional scan testing environment because handling unknowns requires special ATE support or test response postprocessing to determine if the test passed. In this paper we solve this problem using a novel technique, X-filter, which removes the effect of unknowns on compacted test response. X-filter achieves this by using only O(mx) additional hardware with mx inputs. (x=maximum number of unknowns that can be tolerated, m=number of bits in the compacted response). Unlike compaction methods that require creation of special codes (Mitra, 2004), (Wohl, 2003), X-filter is more flexible in terms of number of errors and unknowns handled, and it does not increase the number of output pins over those used by the error correcting code itself

X-Press Compactor for 1000x Reduction of Test Data

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

Compressed pattern diagnosis for scan chain failures

In scan based designs, 10%-30% defects are in scan chains. Hence scan chain fault diagnosis becomes an important process for silicon debug and yield ramp up. With embedded compression techniques getting popular, chain diagnosis on devices with the embedded compression techniques becomes a challenge. In this paper, we provide a general methodology that can be applied for performing chain diagnosis in the context of any embedded compression techniques with any existing chain diagnosis algorithms. The proposed methodology enables seamless reuse of the existing chain diagnosis infrastructure with compressed test data. Experimental results show that with compressed patterns, the chain diagnosis resolution can be enhanced up to one order of magnitude with only 25% of failure cycles collected from ATE, compared to the diagnosis results with uncompressed patterns

Signature Based Diagnosis for Logic BIST

This paper presents a new approach for performing logic BIST diagnosis exclusively using MISR signatures. Unlike conventional logic BIST diagnosis approaches which require either huge test time or complicated logic BIST design and ATE flow, signature based diagnosis does not require dynamically changing MISR operations for each failing device. Our experimental data shows that signature based diagnosis can achieve similar diagnosis resolution with manageable diagnosis run time while eliminating most of the complexity associated with the traditional approach to logic BIST diagnostics.

At-speed built-in self-repair analyzer for embedded word-oriented memories

CRESTA is a built-in self-repair analyzer (BISRA) used for repair of bit-oriented memories, which can repair all repairable bit-oriented memories with available spare resource. This paper enhances CRESTA to support embedded word-oriented memories. Within each read cycle of at-speed memory BIST, the analyzer is able to handle multiple-bit failure in a word-oriented memory. Furthermore, to reduce area overhead, the proposed analyzer is reconfigurable to process all repair strategies in serial. To cover all repair strategies efficiently, we propose a branch and bound algorithm to select repair strategies.

Automatic Test Pattern Generation for Interconnect Open Defects

We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (open- via defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for parameter extraction (PEX) and test generation (ATPG). A highly optimized branch-and bound algorithm to determine the values to be assigned to the aggressor lines is used to reduce both the ATPG efforts and the number of aborts. The resulting test sets are smaller and achieve a higher defect coverage than stuck-at n-detection test sets, and are robust against process variations.