Hugo M. Teixeira

Base-band derived volterra series for power amplifier modeling

This paper proves that the traditional way of deriving power amplifier low-pass equivalent complex-signal Volterra models from their original band-pass RF real-signal Volterra models is too restrictive, and so does not lead to an optimal model. Then, it proposes a much richer alternative approach. Instead of deriving the base-band Volterra model from the RF Volterra model, we started by a general Volterra series expansion of a complex-signal to only then impose the restrictions of odd parity required by the low-pass equivalent polynomial approximation. This way, not only we prove that the theoretical reticence that was raised to similar approaches previously proposed for the memoryless polynomial and the memory polynomial were unfounded, as experimental results fully justified this novel approach.

Novel Extraction of a Table-Based I–Q Behavioral Model for High-Speed Digital Buffers/Drivers

An efficient and accurate table-based behavioral model extraction for high-speed input/output (I/O) buffer behavior is presented in this paper. The nonlinear current-voltage (I-V) and charge-voltage (Q-V) functions describing the graybox model structure are extracted via least-squares methods using identification signals recorded from large signal transient simulation. The resulting continuous time-domain model is easily implemented as lookup table and leads to an increase in modeling accuracy, and a decrease in computation time, as is demonstrated in this paper. Finally, its application in a realistic signal integrity scenario is presented, demonstrating a superior performance compared to that of the I/O buffer information specification model.

Validation by Measurements of an IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern system-in-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysis.

Behavioral Modeling of IC Memories From Measured Data

This paper addresses the generation of behavioral models of digital integrated circuits (ICs) for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network. The modeling procedure is demonstrated for a commercial nor Flash memory in 90-nm technology housed by a specifically designed test fixture.

Characterization and modeling of the power delivery networks of memory chips

This paper focuses on the power delivery characterization of high-speed IC memories by means of on-chip measurements. A systematic analysis of the measurement setup, of the effects of chip biasing and of the use of the measured responses to develop models defined by simplified circuit equivalents is given. All the results collected in the paper are based on real measurements carried out on a commercial 90nm flash memory.

A new predistorter model based on power amplifier physical knowledge

This paper presents a new power amplifier (PA) linearizer model whose topology has support on the physical recursive behavior of the general PA electronic circuit. The resulting model presents a topology that, in its essence, is non recursive, which makes it suited for an easy implementation on digital hardware devices (such as FPGAs and DSPs). Validation tests were performed on a 900 MHz PA excited with WCDMA-3GPP signals and comparison with other linearizer models demonstrated its excellence. Due to its support on the PA physical behavior, the proposed predistorter model has the potential to be an adequate linearizer for a wide range of PA device technologies and excitation signals.