Wael Dghais

Reduced-Order Parametric Behavioral Model for Digital Buffers/Drivers With Physical Support

In this paper, we present a new behavioral model for high-speed digital output buffers/drivers. In the conceived model, the output currents relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by the measurements as well as the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the devices electrical behavior from transient input-output data. A simple single-step identification procedure is conceived to extract a model that proved to be stable and capable of significantly improving the simulation speed and accuracy of prediction. Finally, the resulting model is validated in a realistic signal integrity simulation setup, and is compared to transistor-level models and to the state-of-the-art input-output buffer information specification model.

A Novel Two-Port Behavioral Model for I/O Buffer Overclocking Simulation

This paper presents the first behavioral model solution to the computationally efficient simulation of digital I/O buffers under overclocking operation. Our physics-based two-port approach relies on predicting the timing signals that control the activation of the drivers output stage. The identified nonlinear dynamic model operators of the input port replace the concatenated fixed step-input describing functions of the previous table-based I/O buffer information specification and of other parametric approaches. The implemented gray-box model produces more accurate results than the previous methodologies when assessing the signal integrity performance of high-speed digital links in normal and overclocking conditions under various input excitations. However, it still preserves the computational efficiency recognized for its behavioral model predecessors.

Novel Extraction of a Table-Based I–Q Behavioral Model for High-Speed Digital Buffers/Drivers

An efficient and accurate table-based behavioral model extraction for high-speed input/output (I/O) buffer behavior is presented in this paper. The nonlinear current-voltage (I-V) and charge-voltage (Q-V) functions describing the graybox model structure are extracted via least-squares methods using identification signals recorded from large signal transient simulation. The resulting continuous time-domain model is easily implemented as lookup table and leads to an increase in modeling accuracy, and a decrease in computation time, as is demonstrated in this paper. Finally, its application in a realistic signal integrity scenario is presented, demonstrating a superior performance compared to that of the I/O buffer information specification model.

Behavioral model for high-speed digital buffer/driver

This paper presents a new behavioral macromodeling approach for high-speed digital output buffers/drivers. Unlike traditional behavioral black-box modeling techniques, our approach consists of modeling digital drivers based on their physical constitution in order to simplify the complexity of the nonlinear parametric relationship and include the package network within the nonlinear model structure. For that, the operation of the driver was analyzed by dividing the problem into a nonlinear static and a linear dynamic part. The resulting model is useful for the signal integrity (SI) analysis and has a good performance in terms of both accuracy and speed.

New Multiport I/O Model for Power-Aware Signal Integrity Analysis

This paper presents a new multiport power-aware behavioral model formulation and extraction for high-speed input/output (I/O) buffers that enable the transient prediction of power and ground bouncing effects under simultaneously switching output (SSO) buffers for signal and power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the I/O buffer information specification (IBIS) buffer issue resolution documents (BIRDs) (i.e., BIRD-95.6 and BIRD-98.3) and the macromodeling via parametric identification of logic gates (Mpilog) (i.e., artificial neural network). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation that integrates both the previous BIRDs with a well-designed characterization and parametric extraction procedure. The accuracy and computational performances of the proposed model is evaluated under a realistic SSO scenario.

Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation

This paper presents a multiport empirical model based on artificial neural network for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about the I/O interfaces nonlinear dynamic behavior are recorded from large signal simulation setup. The models functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port.

UTTB FDSOI Back-Gate Biasing for Low Power and High-Speed Chip Design

The paper presents the advantage of the Ultra-thin body and buried-oxide (BOX) (UTTB) fully depleted silicon-on-insulator (FDSOI) as an enabling transistor technology through effective back-gate biasing schemes to overcome the challenges that arises from downscaling bulk CMOS technology for low power and high-speed design tradeoff. The effects of the back-gate bias methodologies that can vary or modulate the substrate bias to adapt the transistor’s threshold voltage are detailed. The design schemes that can be used with this technology are described to illustrate their applications with UTTB FDSOI transistor.

Memristor state-space embedding

This paper presents a procedure for the determination of the dimensionality of the state space of a memristive device. The state space dimensionality of a device corresponds to the minimum number of time delayed values/derivatives of the voltage and current required to represent the device dynamics for a specified set of inputs. The algorithm is based on the observed time domain voltage-current (i.e. input-output) data which is obtained by measurement. The determination of the state space dimensionality is important to achieve a single-valued input-output multivariate mapping between the device outputs as a function of the embedding variables. In this paper, this will be accomplished using an embedding technique, based on the false nearest neighbor principle.

Neuro-Fuzzy Nonlinear Dynamic Modelling for Signal Integrity Simulation

This chapter presents a multiport empirical model for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about I/O interface are recorded from large signal simulation setup. The model’s functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port. Moreover, a comparative analysis between the artificial neural networks (ANNs) and adaptive neuro-fuzzy inference (ANFIS) models by exploring their modelling capabilities regarding the mathematical structures and identification algorithms in providing an accurate and computational effective behavioral model for the I/O buffers nonlinear dynamic behavior is investigated. The proposed model of the two-port I/O buffer is extracted from observable large-signal I/O current and voltages transient data. The training and computational performances along with the prediction accuracy of both modelling approaches are evaluated. The ANFIS model has better prediction accuracy by improving the normalized mean squared error (NMSE) by −13.5 dB while reducing by 11.66% the parameters’ number in cross-validation signal integrity scenario.

Real Time Modelling and Processing

This chapter outlines a general overview of the real-time modelling and processing requirements by exploring the fundamental and perspectives concepts of the real time processing challenges. The workflow of a computationally efficient and accurate real time modelling algorithm is presented and analyzed for both computer large scale electronic device real time simulation and when the algorithm is embedded in a hardware platform where the CPU and memory resources need to be carefully considered. The advantages and real time processing applications of the future neurocomputation or processing in memory, enabled by the recent research on memristive nanoscale devices that eliminates the gap between the memory and processing unit, are presented. Moreover, the requirements and the challenges for generating a high-level abstraction modeling algorithms that balance the tradeoffs between computational complexity and predictive accuracy are described and discussed for electronic device real time computer simulation, control and automation.