Huilong Xu

Repeated growth and bubbling transfer of graphene with millimetre-size single-crystal grains using platinum

Large single-crystal graphene is highly desired and important for the applications of graphene in electronics, as grain boundaries between graphene grains markedly degrade its quality and properties. Here we report the growth of millimetre-sized hexagonal single-crystal graphene and graphene films joined from such grains on Pt by ambient-pressure chemical vapour deposition. We report a bubbling method to transfer these single graphene grains and graphene films to arbitrary substrate, which is nondestructive not only to graphene, but also to the Pt substrates. The Pt substrates can be repeatedly used for graphene growth. The graphene shows high crystal quality with the reported lowest wrinkle height of 0.8 nm and a carrier mobility of greater than 7,100 cm2 V−1 s−1 under ambient conditions. The repeatable growth of graphene with large single-crystal grains on Pt and its nondestructive transfer may enable various applications.

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage.

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.

Growth and Performance of Yttrium Oxide as an Ideal High-κ Gate Dielectric for Carbon-Based Electronics

High-quality yttrium oxide (Y(2)O(3)) is investigated as an ideal high-kappa gate dielectric for carbon-based electronics through a simple and cheap process. Utilizing the excellent wetting behavior of yttrium on sp(2) carbon framework, ultrathin (about few nm) and uniform Y(2)O(3) layers have been directly grown on the surfaces of carbon nanotube (CNT) and graphene without using noncovalent functionalization layers or introducing large structural distortion and damage. A top-gate CNT field-effect transistor (FET) adopting 5 nm Y(2)O(3) layer as its top-gate dielectric shows excellent device characteristics, including an ideal subthreshold swing of 60 mV/decade (up to the theoretical limit of an ideal FET at room temperature). The high electrical quality Y(2)O(3) dielectric layer has also been integrated into a graphene FET as its top-gate dielectric with a capacitance of up to 1200 nF/cm(2), showing an improvement on the gate efficiency and on state transconductance of over 100 times when compared with that of its back-gate counterpart.

A high-performance top-gate graphene field-effect transistor based frequency doubler

A high-performance top-gate graphene field-effect transistor (G-FET) is fabricated, and used for constructing a high efficient frequency doubler. Taking the advantages of the high gate efficiency and low parasitic capacitance of the top-gate device geometry, the gain of the graphene frequency doubler is increased about ten times compared to that of the back-gate G-FET based device. The frequency response of the frequency doubler is also pushed from 10 kHz for a back-gate device to 200 kHz, at which most of the output power is concentrated at the doubled fundamental frequency of 400 kHz.

Quantum Capacitance Limited Vertical Scaling of Graphene Field-Effect Transistor

A high-quality Y2O3 dielectric layer has been grown directly on graphene and used to fabricated top-gate graphene field-effect transistors (FETs), and the thickness of the dielectric layer has been reduced continuously down to 3.9 nm with an equivalent oxide thickness (EOT) of 1.5 nm and excellent insulativity. By measuring CV characteristics of two graphene FETs with different gate oxide thicknesses, the oxide capacitance and quantum capacitance are retrieved directly from the experimental CV data without introducing any additional fitting process and parameters, yielding a relative dielectric constant of κ=10 for Y2O3 on graphene and an oxide capacitance of about 2.28 μF/cm2. It is found that for a rather large gate voltage range, this oxide capacitance is comparable and sometimes even larger than the quantum capacitance of graphene. Since the total gate capacitance is determined by the smaller of the oxide and quantum capacitance, our results show that not much further improvement can be gained via further vertical scaling down of the gate oxide, suggesting that Y2O3 may be the ultimate dielectric material for graphene. It is also shown that the Y2O3 gate dielectric layer with EOT of 1.5 nm may also satisfy the ultimate lateral scaling requirement on the gate length of graphene FET and be used effectively to control a graphene FET with a gate length as small as 1 nm.

Top-Gated Graphene Field-Effect Transistors with High Normalized Transconductance and Designable Dirac Point Voltage

High-performance graphene field-effect transistors (G-FETs) are fabricated with carrier mobility of up to 5400 cm(2)/V·s and top-gate efficiency of up to 120 (relative to that of back gate with 285 nm SiO(2)) simultaneously through growing high-quality Y(2)O(3) gate oxide at high oxidizing temperature. The transconductance normalized by dimension and drain voltage is found to reach 7900 μF/V·s, which is among the largest of the published graphene FETs. In an as-fabricated graphene FET with a gate length of 310 nm, a peak transconductance of 0.69 mS/μm is realized, but further improvement is seriously hindered by large series resistance. Benefiting from highly efficient gate control over the graphene channel, the Dirac point voltage of the graphene FETs is shown to be designable via simply selecting a gate metal with an appropriate work function. It is demonstrated that the Dirac point voltage of the graphene FETs can be adjusted from negative to positive, respectively, via changing the gate material from Ti to Pd.

Measurements and microscopic model of quantum capacitance in graphene

Metal-oxide-semiconductor (MOS) structures based on graphene were fabricated with ultrathin Y2O3 films as the top gate oxide. While the quantum capacitance of graphene was measured using the MOS structure and shown to agree well with theory for ideal graphene at large channel potential, it deviates significantly from theory near the Dirac point. A general microscopic capacitance model is developed and used to describe the quantum capacitance anomaly near the Dirac point. Excellent agreement with experiment results was achieved using this model and key parameters including potential fluctuation and local carrier density fluctuation were retrieved.

High-performance n-type carbon nanotube field-effect transistors with estimated sub-10-ps gate delay

High-performance top-gated n-type single-walled carbon nanotube (CNT) field-effect transistors (FETs) have been fabricated using scandium contacts and HfO2 gate oxide and are benchmarked against the state-of-the-art n-type Si metal-oxide semiconductor FETs. Two key device metrics, the intrinsic gate-delay (CV∕I) and energy-delay product (CV∕I⋅CV2) per unit width, of the n-type CNT FETs are found to show significant improvement over the Si devices. In particular, the gate-delay time is estimated to be 2.1ps for an n-type CNT FET which is based on a CNT with a diameter of 1.1nm and a channel length of 220nm.

Batch-fabricated high-performance graphene Hall elements

Hall elements are by far the most widely used magnetic sensor. In general, the higher the mobility and the thinner the active region of the semiconductor used, the better the Hall device. While most common magnetic field sensors are Si-based Hall sensors, devices made from III-V compounds tend to favor over that based on Si. However these devices are more expensive and difficult to manufacture than Si, and hard to be integrated with signal-processing circuits for extending function and enforcing performance. In this article we show that graphene is intrinsically an ideal material for Hall elements which may harness the remarkable properties of graphene, i.e. extremely high carrier mobility and atomically thin active body, to create ideal magnetic sensors with high sensitivity, excellent linearity and remarkable thermal stability.

Self-Aligned U-Gate Carbon Nanotube Field-Effect Transistor with Extremely Small Parasitic Capacitance and Drain-Induced Barrier Lowering

A novel self-aligned U-gate structure for carbon nanotube (CNT) field-effect transistors (FETs) is introduced and shown to yield excellent dc properties and high reproducibility that are comparable with that of the best CNT FETs based on the previously developed self-aligned device structures. In particular the subthreshold swing of the U-gate FET is 75 mV/dec and the drain-induced barrier lowering is effectively zero, indicating that the electrostatic potential of the whole CNT channel is most efficiently controlled by the U-gate and that the CNT device is a well-behaved FET. Moreover the high-frequency response of the U-gate FET is investigated, and the parasitic capacitance of the device is measured and shown to be one magnitude smaller than that of the previously developed self-aligned device structures. Direct frequency domain measurements show that the U-gate CNT FETs can operate up to 800 MHz, which is also higher than previously reported values. The large improvement in the device high-frequency behavior is largely due to the replacement of the high-κ dielectric material between the source/drain and the gate by a vacant space with κ ≈ 1, and the significant reduction in the device parasitic capacitance renders the U-gate CNT FETs promising for rf applications.