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Dive into the research topics where Xiaofeng Huang is active.

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Featured researches published by Xiaofeng Huang.


visual communications and image processing | 2014

Fast algorithm of coding unit depth decision for HEVC intra coding

Xiaofeng Huang; Huizhu Jia; Kaijin Wei; Jie Liu; Chuang Zhu; Zhengguang Lv; Don Xie

The emerging high efficiency video coding standard (HEVC) achieves significantly better coding efficiency than all existing video coding standards. The quad tree structured coding unit (CU) is adopted in HEVC to improve the compression efficiency, but this causes a very high computational complexity because it exhausts all the combinations of the prediction unit (PU) and transform unit (TU) in every CU attempt. In order to alleviate the computational burden in HEVC intra coding, a fast CU depth decision algorithm is proposed in this paper. The CU texture complexity and the correlation between the current CU and neighbouring CUs are adaptively taken into consideration for the decision of the CU split and the CU depth search range. Experimental results show that the proposed scheme provides 39.3% encoder time savings on average compared to the default encoding scheme in HM-RExt-13.0 with only 0.6% BDBR penalty in coding performance.


IEEE Transactions on Multimedia | 2013

On a Highly Efficient RDO-Based Mode Decision Pipeline Design for AVS

Chuang Zhu; Huizhu Jia; Shanghang Zhang; Xiaofeng Huang; Xiaodong Xie; Wen Gao

Rate distortion optimization (RDO) is the best known mode decision method, while the high implementation complexity limits its applications and almost no real-time hardware encoder is truly full-featured RDO based. In this paper, first, a full-featured RDO-based mode decision (MD) algorithm is presented, which makes more modes enter RDO process. Second, the throughput of RDO-based MD pipeline is thoroughly analyzed and modeled. Third, a highly efficient adaptive block-level pipelining architecture of RDO-based MD for AVS video encoder is proposed which can achieve the highest throughput to alleviate the RDO burden. Our design is described in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18- μm CMOS technology with 232 K logic gates and 85 Kb SRAMs. The implementation results validate our architectural design and the proposed architecture can support real time processing of 1080P@30 fps. The coding efficiency of our adopted method far outperforms (0.57 dB PSNR gain in average) the traditional low-complexity MD (LCMD) methods and the throughput of our designed pipeline is increased by 11.3%, 19% and 17% for I, P and B frames, respectively, compared with the existed RDO-based architecture.


visual communications and image processing | 2015

An adaptive inter CU depth decision algorithm for HEVC

Jie Liu; Huizhu Jia; Guoqing Xiang; Xiaofeng Huang; Binbin Cai; Chuang Zhu; Don Xie

The emerging High-Efficiency Video Coding (HEVC) standard has introduced a number of new coding tools, such as a quad-tree based coding unit (CU). The quadtree-structured coding unit achieves significant coding efficiency improvements compared to H264/AVC. However, the complexity of CU depth decision associated with Rate-Distortion (R-D) cost computation dramatically increased. In order to alleviate the computational burden in HEVC inter coding, a fast CU depth decision algorithm is proposed in this paper. Firstly, zero CU detection method for HEVC is proposed as early termination algorithm. Secondly, the CU depth pruning strategies are adaptively determined according to standard deviation of statistic spatiotemporal depth information. Finally, when the neighbors are not available or have a very weak correlation, edge gradient of current coding tree unit (CTU) is considered as main factor for CU depth pruning method. Experimental results demonstrate that, compared with the original HM16.0 implementation, the proposed algorithm achieves about 40.5% encoding time saving with ignorable coding performance degradation.


advances in multimedia | 2014

An Adaptive Perceptual Quantization Algorithm Based on Block-Level JND for Video Coding

Guoqing Xiang; Xiaodong Xie; Huizhu Jia; Xiaofeng Huang; Jie Liu; Kaijin Wei; Yuanchao Bai; Pei Liao; Wen Gao

It has been widely demonstrated that integrating efficient perceptual measures into traditional video coding framework can improve subjective coding performance significantly. In this paper, we propose a novel block-level JND just-noticeable-distortion model, which has not only adjusted pixel-level JND thresholds with more block characteristics, but also integrated them into a block-level model. And the model has been applied for adaptive perceptual quantization for video coding. Experimental results show that our model can save bit rates up to 24.5% on average with negligible degradation of the perceptual quality.


computational science and engineering | 2014

Highly Efficient Local Non-Texture Image Inpainting Based on Partial Differential Equation

Chuang Zhu; Huizhu Jia; Meng Li; Xiaofeng Huang; Xiaodong Xie

Image in painting has been a popular study point in recent years and a number of strategies have been developed. Partial differential equation (PDE) image in painting approach often acts as a fundamental building block in this area. However, the high computing load limits the application of PDE-based image in painting, especially in mobile terminal. In this paper, first an enhanced Curvature-Driven Diffusions (ECDD) model is proposed to improve the repairing performance. Then a fast local non-texture in painting scheme is performed based on ECDD and total variation (TV) to make the computing of the PDE-based image in painting more efficient. The experimental results show that the proposed strategy not only can repair the long disconnected objects more accurately, but also can greatly shorten the iteration time of image in painting.


advances in multimedia | 2013

A Novel Hardware-Based UHD Video Up-Scaler Based on Local Structure Estimation

Hang Sun; Shengfu Dong; Xiaodong Xie; Meng Li; Xiaofeng Huang; Wen Gao

A novel HW-based video up-scaling method proposed in this paper performs the video image up-scaling. Based on the geometry similarity between the original image and the target image, the proposed algorithm produces new pixels by exploiting the directional weights from the errors estimated by a preset interpolation model in the local area, and using the weights to combine two pixel values predicted by the same model. The algorithm can well preserve the local structure, the edge sharpness in particular, and effectively reduce artifacts such as jaggies and ringings. Based on this method, an efficient HW architecture is developed which is capable of processing at real-time up-scaling to HD or UHD@30fps. Experimental results demonstrate that the proposed method even outperforms some methods using more complex algorithms in both objective and subjective image qualities. In addition, the low complexity of the algorithm simplifies the hardware implementation, which makes real-time enlargement of video image practical.


international conference on multimedia and expo | 2014

A low-complexity hardware-oriented mode decision scheme based on rate-distoration estimation

Meng Li; Chuang Zhu; Yuan Li; Xiaofeng Huang; Huizhu Jia; Xiaodong Xie; Wen Gao

Video compression plays an important role in mobile applications, because more and more people use video to communicate with each other (like video call etc). However, the resources (energy, memory etc.) on mobile devices are limited, thus how to achieve a high coding performance in these devices becomes a big challenge. The recent standards such as H.264, HEVC and audio video coding standard (AVS) employ Rate distortion optimization (RDO) to select the best coding modes, however it results in extremely high computational complexity. This work presents a hardware friendly mode decision (MD) scheme. First, hardware-oriented RDcost estimation method is proposed by using least squares technique to reduce computational burden of RDO-based MD. Second, reconstructed-original (REC-ORG) united intra prediction scheme is presented to break the data dependency, while maintaining high coding performance. Third, highly efficient MD pipeline architecture is put forward to enhance MD processing capacity. The coding efficiency of our adopted MD scheme far outperforms (0.402 dB PSNR gain in average) the traditional SAD methods and the throughput of our designed pipeline is increased by 29%, 23% and 23% for I, P and B frames, respectively, compared with the existed RDO-based architecture.


advances in multimedia | 2014

A Background Modeling Scheme Based on High Efficiency Motion Classification for Surveillance Video Coding

Pei Liao; Xiaofeng Huang; Huizhu Jia; Kaijin Wei; Binbin Cai; Guoqing Xiang; Don Xie

Recently, high-efficiency video coding becomes more and more demanded as the explosive requirements of network bandwidth and storage space for surveillance video applications. In this paper, we propose a background modeling scheme based on high efficiency motion classification. Firstly, pixels at each location are classified into three motion states, namely the static, the gentle motion and the severe motion states, according to the motion vectors of the corresponding current block and neighboring blocks. Then based on the classification and pixel differential value, the segmentation is performed for the co-located pixels in the training frames, and the mean pixel value of each segment can then be calculated. Finally, the background modeling frame can be obtained by an optimized weighted average of the segmented mean pixel values. Experimental results show that our proposed scheme achieves an average PSNR gain of 0.65dB than the AVS surveillance baseline video encoder, and it gets the best performance among several high efficiency background modeling methods in fast motion and large foreground sequences.


international conference on multimedia and expo | 2013

A highly efficient external memory interface architecture for AVS HD video encoder

Xiaofeng Huang; Chuang Zhu; Lei Zhang; Kaijin Wei; Huizhu Jia; Don Xie; Wen Gao

This paper presents a highly efficient external memory interface architecture to improve memory bandwidth utilization for AVS HD video encoder. Both burst and bank interleaved SDRAM accesses are intelligently adopted in the memory interface design. Our proposed architecture is composed of an address mapping layer and an arbitration layer. In the address mapping layer, according to the data request pattern and quantity, the clients in the encoder are divided into four groups which are assigned to different banks of the SDRAM. In each group, efficient address mapping schemes are proposed to minimize inner client overhead. In the arbitration layer, a straightforward group-based interleaved arbitration scheme is proposed to minimize inter client overhead. Experimental results show that the data access overhead cycles of our proposed interface design are reduced significantly and the bandwidth utilization is improved by up to 10% compared to the tile-linear address mapping scheme.


Journal of Real-time Image Processing | 2016

Fast algorithms and VLSI architecture design for HEVC intra-mode decision

Xiaofeng Huang; Huizhu Jia; Binbin Cai; Chuang Zhu; Jie Liu; Mingyuan Yang; Don Xie; Wen Gao

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