Hun Shen Ng

Impact life prediction modeling of TFBGA packages under board level drop test

Abstract Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.

Board level drop test and simulation of TFBGA packages for telecommunication applications

Reliabilit!- perfonnance of IC packages during drop impact is critical, especially for handheld electronic products. Currently. thcrc is no detailed test standard in the industry to advise on the procedures for board level dmp test. nor there is any model Ilia1 providcs good correlation with experimental ineasiircinents of acceleration and impact life. In this paper; detailed drop tests and simulations are pcrfonned on TFBGA (Thin-profile Fine-pitch BGA) and VFBGA (Vey-thinprofile Fine-pitch BGA) packages at board level using testing procediires developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and iueclwnical shock during impact. The critical solder ball is obsewed to occur at the outennost comer solder .joint_ and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically. to understand the effects of drop heightl drop oricntation, number of PCB mounting screws to fixture. position of component on board: PCB bending: solder material, and etc. Drop height, fclt thickness, and contact conditions are used to fine-tune the shape aud level of shock pulse required. Board level drop test can be better controlled. compared with system or product level test such as impact of mobile phone. which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At tlie same time, dynamic simulation is perfonncd to compare with esperiniental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estiinatc the number of drops to failure for a package. For the correlation cases studied. the nminmm nonual peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within M drops, for a typical test of 50 drops. With this new model, a failure-free state can be detennined, and drop test performance of new package design can be quantified. and fuliher enhanced through modeling. This quantitative approach is different from traditional qualitative modeling. as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test ,and thennal cycling test. Different design guidelines should be considered, depcnding on application and area of concern

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

Abstract For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.

Design for enhanced solder joint reliability of integrated passives device under board level drop test and thermal cycling test

The integrated passives device (IPD) is an advanced substrate with embedded passives. The device is mounted to the board with lead-free solder joints. Detailed solder joint reliability models are established for both drop test and thermal cycling test for IPD packages. For drop test, the critical solder joints are observed along the outermost row in the PCB length direction. For thermal cycling test, the critical solder joint is observed at the outermost package corner, with possible failure along the solder/IPD pad interface. The distance to neutral point effect is dominant for IPD structures under drop test and thermal cycling tests. However, drop test performance is more dependent on PCB geometry, compared with the thermal cycling test. Drop test and thermal cycling test have different failure mechanisms and distinct failure modes.

Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA

The semiconductor industry is driving toward lead-free solder due to environmental concern and legislation requirement. The industry has also concluded that SnAgCu solder alloy so far is the best lead-free alternative to SnPb solder. Therefore, most existing and new packages have to be tested and qualified using lead-free solder. One of the critical concerns is board level solder joint reliability during thermal cycling test. In this paper, the methodology for an absolute life prediction is described for virtual qualification of packages. A good absolute fatigue life prediction requires an appropriate solder creep model and actual test data on packages. Two new sets of lead-free Anands constants for SnAgCu solder are introduced for creep models. These Anands creep models are compared with other lead-free and eutectic solder model and the relative design trend is similar. A fatigue corrective factor is introduced to integrate the different solder models together for convenient relative design enhancement with acceptable range of absolute life prediction. These fatigue corrective factors can also be used to compare different finite element modeling assumptions such as element size and solution time step. Subsequently, design analysis is performed to study the effects of 11 key package dimensions and material properties. It is found that the relative design trend for packages with lead-free and eutectic solder is similar. Therefore, the design guidelines established for the previous eutectic solder is still valid for lead-free solder.

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

Abstract For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Abstract Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.

Board-level solder joint reliability analysis of thermally enhanced BGAs and LGAs

Thermally enhanced ball grid arrays (BGAs) are designed to have reduced thermal resistance through features such as heat slug, heat spreader, and thermal solder joints. This paper studies the design comparison of five types of thermally enhanced BGAs, i.e., conduction cooled BGA (C/sup 2/BGA), metal-core BGA, exposed-die land grid array (LGA), slug LGA, and spreader LGA. The solder joint reliability performance of thermally enhanced BGAs is benchmarked with conventional thin-profile fine-pitch ball grid array (TFBGA). Both global and local three-dimensional finite-element analysis (FEA) models are established to predict the fatigue life of solder joints during thermal cycle testing. Detailed pad design with realistic geometry of solder balls and nonlinear material properties are considered in the model. The fatigue model is based on a modified Darveauxs approach with nonlinear viscoplastic analysis of solder joints. For the test vehicles studied, the critical solder joints are located near the package corner. Design variations investigated include the effects of key package dimensions and material properties. Design variations are mainly reported using C/sup 2/BGA package as the trend for the other four thermally enhanced BGAs was similar. The choice of mold compound (MC) material is critical, and a material with higher coefficient of thermal expansion (CTE/sub 1/) and lower modulus is preferred. Die size, die attach, and slug-attach material have little effect on solder joint reliability. It is observed that there is good correlation of fatigue life between modeling prediction and thermal cycle testing for C/sup 2/BGA. Reliability of C/sup 2/BGA thermal solder joints is proven to be excellent, and heat can be effectively conducted away from the die to the PCB. This is crucial to the design of C/sup 2/BGA. In addition, solder joint fatigue life is found to be related to package warpage induced during thermal cycling test. A design with less package warpage usually has a longer fatigue life.

Comprehensive hygro-thermo-mechanical modeling and testing of stacked die BGA module with molded underfill

Package reliability is a great concern in developing new advanced packages. This paper presents some of the modeling and testing activities for the design of mixed flip-chip (FC)-wire bond (WB) stacked die BGA module with molded underfill (MUF). The success of the MUF application depends on its performance in thermal shock (TS) test and pressure cooker test (PCT). Mechanical properties (modulus and adhesion strength) of MUF after post mold cure (PMC), reflow and PCT are measured. Shear strength between die and MUF under various temperature and moisture conditions are also characterized. The results show that reflow process and PCT degrade the material properties and adhesion strength. Hygro-mechanical properties, i.e. coefficient of moisture expansion (CME) and saturated moisture concentration (C/sub sat/), are also measured. Based on the measured mechanical and moisture properties, a combined hygro-mechanical and thermo-mechanical stress modeling is performed on the FC-WB stacked die BGA package to compare three types of MUF materials at various temperatures (-40/spl deg/C,25/spl deg/C,121/spl deg/C, and 150/spl deg/C) PCT condition. It is observed that MUF-D3 material induces the lowest stresses on the die active surface. Die stresses induced by MUF with that of conventional mold compound and underfill materials are also compared. The analysis helps in material selection of MUF to enhance the die and package reliability of BGA module.

Design for standard impact pulses of drop tester using dynamic simulation

Board level solder joint reliability during drop impact is a great concern to semiconductor and electronic product manufacturers, especially for handheld or portable telecommunication devices. A new JEDEC standard for board level drop test of handheld electronic products was released to specify the drop test procedure and conditions. The standard recommends a specific input shock pulse to the PCB subassembly. However, the impact pulse is a complex function of various drop tester design parameters such as the drop block, absorbing material, strike surface materials and dimensions, as well as different testing conditions such as drop height. Therefore, many time-consuming experimental trial-and-errors are required to calibrate and characterize a drop tester to achieve the required impact pulse before actual drop testing can be performed. Thus, dynamic simulation using free-fall drop model is a useful tool to provide design guidelines to achieve the required impact pulse, and to shorten the drop tester characterization process considerably. It is found that the peak acceleration and pulse duration of the impact pulse are strongly affected by the drop block density and thickness as well as absorbing surface modulus and thickness. The drop height affects the peak acceleration but is insignificant on the pulse duration. An empirical relationship is developed to determine the different designs parameters on the peak acceleration and pulse duration. However, in a drop tester, the drop block and the strike surface are usually design constraints. The design parameters that can be varied to achieve the desired impact pulse are the absorbing material and dimensions as well as the drop height. Therefore, a design flowchart is developed to calibrate and characterize the drop tester to achieve the desired impact pulse. The settings of impact pulses for various JEDEC levels A to G are then determined numerically, which are useful references for drop testing engineers.