Jerome Teysseyre

Combined effects of humidity and thermal stress on the dielectric properties of epoxy-silica composites

Abstract We report on the effects of hydrothermal ageing on the dielectric properties of epoxy-silica composites used for microelectronic packaging. The study was carried out for samples with various degrees of curing. Epoxy compounds were subjected to moisture exposure (standard JEDEC procedures) and consecutive thermal stress (240°C). Changes in the dielectric constant and in the loss factor were measured in the 100 Hz–100 kHz frequency range. It is found that water absorption increases with curing. After ageing the dielectric constant is decreased and the loss factor increased. Cured materials have a higher resistance against hydrothermal ageing.

Dielectric properties of epoxy/silica composites used for microlectronic packaging, and their dependence on post-curing

We studied the dielectric properties (dielectric constant and loss factor) of epoxy molding compounds used for electronic packaging, as a function of frequency (100 Hz–100 kHz) and temperature (25–100 °C). Studies were performed for samples with different formulations (various silica and carbon black contents). At room temperature a loss peak is found at 50 kHz, whose intensity is enhanced by carbon black addition. Additional loss is detected below 1 kHz when the temperature is increased up to 100 °C. We also studied the influence of post-mold curing time (0–12 h at 165 °C) on the dielectric properties. The dielectric constant monotonically decreases with post-mold cure to level off to a minimum value for long post-cure durations. The loss factor first increases for short post-curing times, and then decreases as post-cure is continued. The origin of loss is discussed with reference to common relaxation processes observed in epoxy polymers.

Comprehensive hygro-thermo-mechanical modeling and testing of stacked die BGA module with molded underfill

Package reliability is a great concern in developing new advanced packages. This paper presents some of the modeling and testing activities for the design of mixed flip-chip (FC)-wire bond (WB) stacked die BGA module with molded underfill (MUF). The success of the MUF application depends on its performance in thermal shock (TS) test and pressure cooker test (PCT). Mechanical properties (modulus and adhesion strength) of MUF after post mold cure (PMC), reflow and PCT are measured. Shear strength between die and MUF under various temperature and moisture conditions are also characterized. The results show that reflow process and PCT degrade the material properties and adhesion strength. Hygro-mechanical properties, i.e. coefficient of moisture expansion (CME) and saturated moisture concentration (C/sub sat/), are also measured. Based on the measured mechanical and moisture properties, a combined hygro-mechanical and thermo-mechanical stress modeling is performed on the FC-WB stacked die BGA package to compare three types of MUF materials at various temperatures (-40/spl deg/C,25/spl deg/C,121/spl deg/C, and 150/spl deg/C) PCT condition. It is observed that MUF-D3 material induces the lowest stresses on the die active surface. Die stresses induced by MUF with that of conventional mold compound and underfill materials are also compared. The analysis helps in material selection of MUF to enhance the die and package reliability of BGA module.

Copper wirebond pull test and reliability characterization with finite element simulation

In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated in term of die stress underneath the wire bond pad area. A new stress index concept is proposed to characterize the overall die stress level underneath bond pad. Based on this concept, a new method to evaluate Cu pull test limit is established with benchmark to current Au wire standard. The methodology is demonstrated through a Cu wire bonded power package, with the extensive work of process development, reliability test, and stress simulation etc.

Hygro-thermo-mechanical modeling of mixed flip-chip and wire bond stacked die BGA module with molded underfill

Package reliability needs to be considered for the design of mixed flip-chip (FC)-wire bond (WB) stacked die BGA module with molded underfill (MUF). The success of the MUF application depends on its performance in thermal shock (TS) test and pressure cooker test (PCT). Mechanical properties (modulus and adhesion strength) of MUF after post mold cure (PMC), reflow and PCT are measured. Shear strength between die and MUF under various temperature and moisture conditions are also characterized. The results show that reflow process and PCT degrade the material properties and adhesion strength. Hygro-mechanical properties, i.e. coefficient of moisture expansion (CME) and saturated moisture concentration (Csat), are also measured. Based on the measured mechanical and moisture properties, a combined hygro-mechanical and thermo-mechanical stress modeling is performed on the FC-WB stacked die BGA package to compare three types of MUF materials at various temperatures (-40degC, 25degC, 121degC and 150degC) and PCT condition. It is observed that MUF-D3 material induces the lowest stresses on the die active surface. Die stresses induced by MUF with that of conventional mold compound and underfill materials are also compared. The analysis helps in material selection of MUF to enhance the die and package reliability of BGA module

New package for CMOS sensors

Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

Board-Level Reliability Performance of Discrete Power Packages

Board-level thermal cycling reliability performance of two buckets of discrete power packages is evaluated by both Finite Element Analysis (FEA) and an actual test. One bucket consists of smaller size packages and the other consists of bigger size packages. The testing condition follows the established industry standard, IPC-9701, with a temperature range of 0°C ~ 100°C. In FEA modeling, the fatigue life of the board solder joint for gate connection is calculated using both the Darveaux method and modified Coffin-Manson method. In actual board-level thermal cycling tests for a typical power PQFN package, real-time monitoring of the sample units was conducted and no failure was observed until 6000 cycles. By comparing the actual reliability testing data, both the Darveaux method and modified Coffin-Manson method are valid and reliable for the PQFN package board-level solder joint reliability assessment. FEA simulation results show that the power discrete packages with the bigger size are more robust than those with the smaller size. Another observation is that power discrete packages with extended pins out from the package body could improve the board-level thermal cycling reliability performance. The board-level solder joint profile is modeled for a rectangular shape pin of the PQFN package using the Surface Evolver tool, which resulted in a comparable profile as the actual samples. Based on the evaluation from both the FEA modeling and actual testing, more robust power discrete packages could be designed and manufactured.

Development of advanced fan-out wafer level package (embedded Wafer Level BGA) packaging

With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology. Fan-out WLP is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate mUltiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation Fanout WLP for advanced packaging solutions .. A new portfolio of next generation package configurations: small outline Fanout WLP, double-side 3D Fan-out WLP and eWLL (embedded Wafer Level Land Grid Array) are developed and characterized. And the reliability study was carried out in depth by experimental approaches. Successful reliability characterization results on different package configurations are reported that demonstrate next generation Fan-out WLP as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions.

Development and characterization of next generation eWLB (embedded Wafer Level BGA) packaging

The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. eWLB is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently eWLB technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation eWLB for advanced packaging solutions. A new portfolio of next generation package configurations: small outline eWLB, double-side 3D eWLB and eWLL (embedded Wafer Level Land Grid Array) are developed and characterized. And the reliability study was carried out in depth by experimental approaches. Successful reliability characterization results on different package configurations are reported that demonstrate next generation eWLB as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions.

Simulation driven physics-of-failure analysis for System-in-Package development

System-in-Package (SiP) which combines different chips and technologies into a single package is a viable solution to meet the rigorous requirements for todays mixed signal system integration. As the level of integration increases, challenges related to product manufacturability and reliability also increases. As a result, design for reliability using CAE (Computer-Aided-Engineering) or FEM (Finite Element Method) simulation is becoming an effective tool in recent years to reduce the development time, cost and manpower. A case study with simulation driven failure analysis during a SiP module development for RF transceiver is demonstrated. Due to structure complexity (27 components) and lack of detailed information from suppliers, some components are simplified in the global package simulation model. Based on simplified global model, design guidelines are provided for package geometry and material selection, which are validated during package qualification for package warpage control and overall reliability, except failure related SAW filters after TC (thermal cycling). With details shared from supplier, SAW filter is actually a small cavity package. First simulation trial focused on solder bump fatigue life estimation showed weak correlation with experimental data, which imply this is not a normal fatigue related issue (although failure seen after TC), and efforts for failure analysis (FA) should also be put on other factors affecting pre-mature failure, e.g. assembly process parameters. Then from substrate mapping, it is identified that failure units mostly located at mold vent side, not the gate side. Further process DOE trials highlighted that lower transfer pressure leads to higher failure rate. With a close collaboration among project leader, process engineers and suppliers, and a creative data digging on experimental results, final relevant model has been built up and inherent mechanism proposed, which linked all the experimental data observed. Based on the clear physics-of-failure analysis, solution and future development guideline provided, and the related product qualified.