Jing-en Luan

Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross-section and dye penetration test.

Modal analysis and dynamic responses of board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to solder joint failure mechanisms. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layers, are studied by comparing and analyzing the dynamic responses.

Novel numerical and experimental analysis of dynamic responses under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. A novel input acceleration (input-G) method is developed to simulate the exact drop test process using ANSYS-LSDYNA software. The model can be applied to simulate the overall impact responses including PCB cyclic bending, which are very critical for understanding of board level drop test.

Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact

Board level solder joint reliability performance during drop test is a critical concern to semiconductor and electronic product manufacturers. A new JEDEC standard for board level drop test of handheld electronic products was just released to specify the drop test procedure and conditions. However, there is no detailed information stated on dynamic responses of printed circuit board (PCB) and solder joints which are closely related to stress and strain of solder joints that affect the solder joint reliability, nor there is any simulation technique which provides good correlation with experimental measurements of dynamic responses of PCB and the resulting solder joint reliability during the entire drop impact process. In this paper, comprehensive dynamic responses of PCB and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed with a multichannel real-time electrical monitoring system, and simulated with a novel input acceleration (Input-G) method. The solder joint failure process, i.e., crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally and numerically that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint fatigue failure. It is proven that the peeling stress of the critical solder joint is the dominant failure indicator by simulation, which correlates well with the observations and assumptions by experiment. Coincidence of cyclic change among dynamic resistance of solder joints, dynamic strains of PCB, and the peeling stress of the critical solder joints indicates that the solder joint crack opens and closes when the PCB bends down and up, and the critical solder joint failure is induced by cyclic peeling stress. The failure mode and location of critical solder balls predicted by modeling correlate well with experimental observation by cross section and dye penetration tests

Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA

The semiconductor industry is driving toward lead-free solder due to environmental concern and legislation requirement. The industry has also concluded that SnAgCu solder alloy so far is the best lead-free alternative to SnPb solder. Therefore, most existing and new packages have to be tested and qualified using lead-free solder. One of the critical concerns is board level solder joint reliability during thermal cycling test. In this paper, the methodology for an absolute life prediction is described for virtual qualification of packages. A good absolute fatigue life prediction requires an appropriate solder creep model and actual test data on packages. Two new sets of lead-free Anands constants for SnAgCu solder are introduced for creep models. These Anands creep models are compared with other lead-free and eutectic solder model and the relative design trend is similar. A fatigue corrective factor is introduced to integrate the different solder models together for convenient relative design enhancement with acceptable range of absolute life prediction. These fatigue corrective factors can also be used to compare different finite element modeling assumptions such as element size and solution time step. Subsequently, design analysis is performed to study the effects of 11 key package dimensions and material properties. It is found that the relative design trend for packages with lead-free and eutectic solder is similar. Therefore, the design guidelines established for the previous eutectic solder is still valid for lead-free solder.

Dynamic responses and solder joint reliability under board level drop test

Board level solder joint reliability during drop test is a great concern to semiconductor and electronic product manufacturers. In this paper, the comprehensive dynamic responses of printed circuit boards (PCBs) and solder joints, e.g., acceleration, strains, and resistance, are measured and analyzed in detail with a multi-channel real-time electrical monitoring system. Control and monitoring of dynamic responses are very important to ensure consistent test results and understand the mechanical behaviors, as they are closely related to the solder joint failure mechanism. The effects of test variables, such as drop height, number of PCB mounting screws, tightness of screws, and number of felt layer, are studied by comparing and analyzing the dynamic responses. A good repeatability of testing can only be achieved when careful attentions are paid on these factors. The relationships among drop height, peak acceleration, pulse duration, and impact energy are unique for a drop tester, and therefore, it should be characterized prior to the reliability tests. The studies also help to determine the requirements of new impact pulse quickly. The bending mode shapes and frequencies of PCB are extracted from dynamic strains and images token by high-speed camera. A real-time dynamic resistance monitoring method is developed to study the solder joint reliability. The solder joint failure process, i.e. crack initiation, propagation, and opening, is well understood from the behavior of dynamic resistance. It is found experimentally that the mechanical shock causes multiple PCB bending or vibration which induces the solder joint crack failure. Cyclic changes of dynamic resistance indicate that the solder joint crack opens and closes when PCB bends up and down.

Effect of silver content and nickel dopant on mechanical properties of Sn-Ag-based solders

In this work, five solder materials of Sn-3.0Ag-0.5Cu (SAC305), Sn-2.0Ag-0.5Cu (SAC205), Sn-1.0Ag-0.5Cu (SAC105), Sn-1.0Ag-0.5Cu-0.05Ni (SAC105Ni0.05) and Sn-1.0Ag-0.5Cu-0.02Ni (SAC105M0.02) were tested using tensile loading at room temperature to investigate the Ag content and Ni dopant effect on solder mechanical properties, respectively. In addition, different testing temperature conditions including -35 deg.C, 25 deg.C, 75 deg.C and 125 deg.C were used for SAC105M0.02 solder to investigate the temperature effect on mechanical properties. Tensile test under different strain rates from 0.000011/s to 0.11/s was conducted to study the strain rate effect on material properties. Test results show that the material properties of modulus, UTS and yield stress increase with strain rate and Ag content, but decrease with temperature. The 500 ppm Ni dopant has the significant effect on material properties of Sn-Ag-based solder than 200 ppm Ni dopant. Lower modulus, yield stress and UTS, higher elongation can be achieved for SAC105M0.05 solder compared to SAC105M0.02 solder. The rate dependent and Ag content dependent material models were developed for Sn-Ag-Cu lead free solders. In addition, the temperature and rate dependent models were developed for SAC105M0.02 solder. The microstructures of different solder alloys were analyzed based on SEM images. It was found that Ag content affects the Ag3Sn intermetallic compound dispersion and Sn grain size. The microstructure of solder alloy has finely dispersed IMC and fine Sn grain size for the high Ag content solder, which make the solder exhibit high strength.

Drop impact life prediction model for wafer level chip scale packages

The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Wafer-level chip scale package (WL-CSP) is the newest technology to compete with CSP and near-CSP packaging, and has evolved under JEDEC MO-211 standard. This bare-die bumped package is able to reduce single-gate logic sizes by as much as 84%, and offer significant area savings, improved package electrical parasitics and power dissipation over leaded CSP and CSP-BGA packages. However, little is known about its mechanical performance under shock impact and how it is compared to its CSP counterparts, which is of utmost importance in handheld electronics. In this paper, a drop impact life prediction model is established for WL-CSP with excellent correlation with experimental values. Critical bump location, crack initiation site and failure mode found in failure analysis shows that the simulation model is able to give accurate qualitative and quantitative prediction and understanding of physics involved in drop impact failure of WL-CSP. With an accurate impact life prediction model, one can further establish design guidelines, such as to determine the largest bumped die allowable to still meet the number of drops before failure occur. Effects of design parameters such as solder bump pitch, solder diameter, solder standoff, and solder material (lead-free vs. eutectic) on solder joint reliability under drop impact testing are discussed in this paper. One key finding is that a smaller bump pitch results in a better drop impact performance, which is verified by both simulation and experiment. Hence, miniaturization of WLCSP with reduction in bump pitch has a positive impact on its board level drop reliability. It is also interesting to note that the distance-to-neutral-point (DNP) effect must be considered in the PCB length direction where the bending mode dominates. This is different from typical thermal cycling where the DNP effect is usually considered in the diagonal direction

Design for standard impact pulses of drop tester using dynamic simulation

Board level solder joint reliability during drop impact is a great concern to semiconductor and electronic product manufacturers, especially for handheld or portable telecommunication devices. A new JEDEC standard for board level drop test of handheld electronic products was released to specify the drop test procedure and conditions. The standard recommends a specific input shock pulse to the PCB subassembly. However, the impact pulse is a complex function of various drop tester design parameters such as the drop block, absorbing material, strike surface materials and dimensions, as well as different testing conditions such as drop height. Therefore, many time-consuming experimental trial-and-errors are required to calibrate and characterize a drop tester to achieve the required impact pulse before actual drop testing can be performed. Thus, dynamic simulation using free-fall drop model is a useful tool to provide design guidelines to achieve the required impact pulse, and to shorten the drop tester characterization process considerably. It is found that the peak acceleration and pulse duration of the impact pulse are strongly affected by the drop block density and thickness as well as absorbing surface modulus and thickness. The drop height affects the peak acceleration but is insignificant on the pulse duration. An empirical relationship is developed to determine the different designs parameters on the peak acceleration and pulse duration. However, in a drop tester, the drop block and the strike surface are usually design constraints. The design parameters that can be varied to achieve the desired impact pulse are the absorbing material and dimensions as well as the drop height. Therefore, a design flowchart is developed to calibrate and characterize the drop tester to achieve the desired impact pulse. The settings of impact pulses for various JEDEC levels A to G are then determined numerically, which are useful references for drop testing engineers.

Challenges for extra large embedded wafer level ball grid array development

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.