Hung-Chang Yu

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.

A 40nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140MHz read speed and data memory with 1M cycles endurance

This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160°C and data storage memory achieves 1M cycles endurance.

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V

To achieve the 180MHz read speed for 4.6 Mb Flash memory, we propose an adaptive WL boost driver (AWBD) and a high-speed sensing-assist (HSSA) scheme to fast activate the word-line and bitline. AWBD reduces 45% word-line rising time. HSSA establishes bitline bias within 500ps under heavy bit-line load. This work implemented in 90nm process and the access time 5.2ns is achieved.