Ku-Feng Lin

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications

This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T_AC) and low RD-V_DDMIN, particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high RD-V_DDMIN and slow T_AC. As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (R_H/R_L) between the high-R state (HRS, R_H) and low-R state (LRS, R_L). ReRAM also have a high R_L, which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited RD-V_DDMIN, and slow T_AC due to high-R_L and small R-ratio; (2) increase in energy due to large set DC-current (I_DC-SET) resulting from wide set-time (T_SET) distribution. This study develops a swing-sample-andcouple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-V_DDMIN and 1.7× faster T_AC across various V_DD, compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off I_DC-SET of faster-T_SET devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves T_AC = 404ns at V_DD = 0.27V and confirms the I_DC-SET cut-off by SBWT.

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Numerous low-supply-voltage (VDD) mobile chips, such as energy-harvesting-powered devices and biomedical applications, require low-VDD on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs cannot achieve low-VDD operation due to insufficient write voltage generated by charge-pumped (CP) circuits at a low VDD, and a lack of low-VDD current-mode sense amplifiers (CSA) [1-4] to overcome read issues in reduced sensing margins, degraded speeds, and insufficient voltage headroom (VHR). Resistive RAM (ReRAM) [4-6] is a promising memory with the advantages of short write time, low write-voltage, and reduced write power compared to Flash and other NVMs. Using a low-VDD CP with relaxed output voltage/current requirements for write operations, ReRAM is a good candidate for on-chip low-VDD NVM if a low-VDD CSA is provided, particularly for frequent-read-seldom-write applications. We develop a body-drain-driven CSA (BDD-CSA) with dynamic BL bias voltage (VBL) and small VHR for larger sensing margins to achieve a lower VDDmin, faster read speed, and better tolerance of read cell current (ICELL) and BL leakage current (IBL-LEAK) variations compared to conventional CSAs. A fabricated 65nm 4Mb ReRAM macro using the BDD-CSA and our CMOS-logic-compatible ReRAM cell [7] achieves 0.5V VDDmin. The BDD-CSA achieves 0.32V VDDmin.

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 1012 cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust and fast low-VDD read scheme. Current-mode sense amplifiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due to an insufficient on-off current difference ( I ON-OFF) and the need for large voltage head room (VHR). This study developed a body-drain-driven (BDD) read scheme to suppress VHR and provide resistance-aware dynamic bitline bias voltage for increasing I ON-OFF. The proposed scheme achieved 2.1 × faster read speed, > 1.7× higher yield, and > 2× longer BL length at 0.5 V VDD than conventional CSAs. A fabricated 65 nm 4 Mb ReRAM macro using the proposed read scheme and our logic-compatible ReRAM cell achieved a 45 ns random read access time at VDD=0.5 V. The proposed sensing scheme also achieved a 0.32 V VDDmin.

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-VDDmin-delay-product embedded ROM for storing fixed programs and data [1]. NOR-ROMs provide low VDD and high speed for small-capacity applications with a short bitline (BL) [2]. However, if read−1 noise can be eliminated, a NAND-ROM is superior [1] for large-capacity storage in standby-dominated low-voltage chips because of smaller area, narrower cell-current (ICELL) distribution, and lower standby current. Static NAND-ROM with short BL [1] achieves small read−1 noise and low VDD with a 33% area penalty. Applying selected precharge [3], driving source-line (SL) [4], or BL-shield [5], [6] schemes to NAND-ROM can eliminate only one of the read−1 noise sources, which are charge sharing, BL leakage, and BL crosstalk. The remaining read−1 noise reduces the sensing margins for reading 1-cells (VSM1) and 0-cells (VSM0) and limits the VDDmin and speed of NAND-ROMs. This paper presents dynamic split source-lines (DSSL) scheme to eliminate read−1 noise and a data-aware sensing reference (DASR) scheme to expand VSM0 to tolerate larger ICELL variations for large-capacity low-voltage NAND-ROM. These schemes enable large-capacity NAND-ROM to achieve lower VDDmin, higher speed, and lower power consumption with small area overhead.

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements

Embedded NAND-type read-only-memory (NAND-ROM) provides large-capacity, high-reliability, on-chip non-volatile storage. However, NAND-ROM suffers from code-dependent read noises and cannot survive at low supply voltages (VDDs). These code-dependent read noises are primarily due to the charge-sharing effect, bitline leakage current, and crosstalk between bitlines, which become worse at lower VDD. This study proposes a dynamic split source-line (DSSL) scheme for NAND-ROM. The proposed scheme overcomes code-dependent read noises while improving the read access time and suppressing the active-mode gate leakage current, with only a 1% area penalty in the cell array. Experiments on a fabricated 256 Kb macro using a 90 nm industrial logic process demonstrate that the proposed DSSL scheme achieves 100% code-pattern coverage under a small sensing margin. Additionally, the DSSL NAND-ROM works with a wide range of supply voltages (1-0.31 V) with a 38%, 45.8%, and 37% improvement in speed, power, and standby current, respectively, at VDD = 1 V.

Low

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read- VDDmin, and slow read access time (TAC) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (IDC-SET) resulting from the wide distribution of write (SET)-times (TSET). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately 1.8+x greater sensing margin for lower VDD min and a 1.7+x faster read speed across a wide VDD range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the IDC-SET of devices with a rapid T SET. The SBWT scheme reduces 99+% of the IDC-SET with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved TAC = 404 ns when VDD=0.27 V and confirmed the IDC-SET cutoff by the SBWT.