Chi-Hsueh Wang

A 0.27mm 2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS

An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.

A 65nm GSM/GPRS/EDGE SoC with Integrated BT/FM

A highly integrated RF transceiver for GSM/GPRS/EDGE application is implemented in a 65nm SOC with BT and FM systems. Techniques are employed to minimize the coupling and interference effects among three wireless systems and results show the sensitivity and the output spectrum stay unchanged. The EDGE digital low-IF receiver achieves −110dBm sensitivity and −9dBm IIP3; while the EDGE polar transmitter achieves an ORFS of −66dB at 400kHz. This transceiver consumes 61/60mA in RX/TX EDGE modes.