Hung-Hsiang Cheng

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.

Frequency dielectric constant and loss tangent extracting of organic material using multi-length microstrip

Organic material using for packaging substrate is selected and multi-length microstrip lines in same trace width are designed and performed on it. Novel formulas deliver to extract dielectric constant and loss tangent varying with frequency for selected organic materials will be shown in this paper. Performances of microstrip lines are measured by Agilent vector network analyzer up to 20 GHz and SOLT calibration used to get two-port S-parameters. Then, novel formulas are used to extract material parameters in ADS software by measurement date.

Through Co-design to optimize power delivery distribution system using embedded discrete decoupling capacitor

As clock speeds increase into the gigahertz regime and rise times decrease into the pico-second regime, the interaction between capacitors and power/ground planes of a package, or board on which they are mounted becomes vitally important to the performance of a power delivery system. Capacitors pose the biggest challenge for integration in packages due to the large capacitance required for decoupling high performance circuits. Although Embedded Passive Substrate (EPS) using thin-film technique was addressed and developed, the actually application without substrate packaging layer increased is difficult. An Embedded Discrete Passive Substrate (EDPS) technology is increasingly drawing attention because of its potentials in addressing system cost reduction by offering smaller size form factor with high level of integration in packaging. In this paper, a embedded discrete capacitor structure was designed and fabricated on organic substrate packaging. Through early engagement and optimization on substrate packaging design, the embedded discrete capacitors could improve the electrical performance of core power distribution system. To validate the feasibility, a test substrate packaging is built. In addition, the simulation results of core power distribution system with EPDS and Copper Wire-Bond (CWB) on time-doamain and frequency-domain demonstrate the electrical performance is better than others..

Advance semiconductor package applied on high efficiency dual-mode DC-DC buck converter

This work analyzes the electrical performance for three different packaging types applied on power management IC (PMIC) using a high efficiency dual-mode DC-DC buck converter. A 600 mA with 93 % efficiency dual-mode DC-DC buck converter is designed and fabricated by TSMC 0.35-μm CMOS process. The chip area is smaller about 2.1 mm2. The packaging parasitic effects of advanced single sided substrates (aS3 package) with wire-bond interconnect / copper pillar bump and fan-out wafer level chip scale package (fan-out WLP) are extracted from the layout drawings using the Ansys Q3D Extractor. A SPICE based circuit model of DC-DC buck converter is applied to determine the power dissipation. The power dissipation of the DC-DC buck converter implemented on aS3 package with wire-bond interconnect / copper pillar bump and fan-out WLP are 20 mW, 6 mW, and 5 mW, respectively. For high efficiency DC-DC buck converter application, aS3 package with copper pillar bump is applicable for medium pin count solutions and low cost packaging technology. Fan-out WLP is applicable for high pin count solutions with small-size and high performance.

Electrical performance analysis of fine line on high density package substrate

This paper presents the electrical characterization of fine line design. For this kind of very thin and narrow fine lines in high density substrate, the trace is no longer lossless or low-loss transmission line and the characteristic impedance is also varying with frequency. This phenomenon on high density substrate will lead to different design guideline from conventional one. In this paper, the electrical performance of the micro-strip line (MSL) with coupling trace, Co-Planar Waveguide (CPW) and Grounded Co-Planar Waveguide (GCPW) three transmission line designs will be analyzed and discussed. For fine pitch fabrication quality control, it is better to keep thick-width-aspect-ratio larger than 1.5. As a result the trace is designed to 3um thick and 2um wide. Impedance, conductor loss, cross-talk and eye diagram for 10mm long trace will be analyzed in this paper. Proper design of line pitch of GCPW to have good signal integrity performance is then demonstrated.

Dielectric Characterization of Ultra-Thin Low-Loss Build-Up Substrate for System-in-Package (SiP) Modules

This work proposes a method based on microstrip multi-size T-resonators to increase the accuracy of extracted dielectric characteristics. The dielectric characteristics of an ultra-thin and low-loss build-up substrate for system-in-package modules are obtained, which closely correspond to the measured S-parameters. An electromagnetic simulation is performed to verify the extracted dielectric characteristics. The proposed method is also used to improve the accuracy of prediction of far-field radiated emission at resonant frequencies from a microstrip component.

Synthesizing SPICE-compatible models of power delivery networks with resonance effect by time-domain waveforms

A novel time-domain approach is proposed to synthesize the broadband equivalent circuit model of the power delivery network based on time-domain reflected (TDR)/transmitted (TDT) waveforms either through time-domain reflectometry measurement or finite-difference time-domain (FDTD) simulation. The step responses of the power delivery network are represented in terms of rational functions by the generalized pencil-of-matrix (GPOM) method. According to the step responses, the macro-pi model with each element represented by the optimum pole-residue forms is derived to model the power delivery networks. The equivalent circuits of the macro-pi model are synthesized by a systematic lumped- model extraction technique. The accuracy of this approach is demonstrated both in frequency- and time-domain.

3D WL MEMS with Various TSV Technologies' Thermo-Mechanical Analysis

The through-silicon-via (TSV) technology is one of the most effective approaches to fulfill the form factor, profile, performance, and 3D interconnect demand of next generation handheld and wearable electronics. The TSV technology has been developed into two categories, the TSV Last and the TSV Middle. In this article, we examined a variety of aspects of the two TSV technologies when applied to 3D wafer level (WL) microelectromechanical systems (MEMS). We investigated the thermo-mechanical behavior of both TSV structures in wafer level package (WLP), through finite-element-analysis (FEA). Stress distribution of the package structures was revealed. The simulation study was also performed on the board level to analyze the extent of warpage of the package. The theoretical results were validated with the corresponding reliability and electrical characteristics investigations.

Scalable Modeling and Measurement of TSV Applied for Efficiency Improvement of a RF PA

A high efficient CMOS class-E power amplifier (PA) by using Quad Flat No-leads (QFN) package combined with Through Silicon Via (TSV) grounding is presented. TSV has much smaller parasitic inductance and resistance than wire-bonds. TSV technology can improve PA efficiency, reduce die size samples and retain low cost in QFN package. The TSV samples are made and measured by using double-side probing technique with a novel calibration method. TSV scalable model is established with good correlation comparing to RF measurement results. Apply the TSV scalable model in the CMOS PA simulation circuit. The simulation results show that TSV delivers obvious reduction in inductance compared to traditional wire-bond and improvement for Power Added Efficiency (PAE).

Improving high-speed signal transmission loss by low conductor surface roughness

The effect of the conductor surface roughness for high-speed signal transmission on package substrate is analyzed. When skin depth becomes smaller than surface roughness at high frequency, the loss of surface roughness becomes important. In this paper, the transmission line patterns are designed on substrate of different conductor surface treatment processes for measuring and comparing the performance. In the GB/s regime, the accurate modeling of conductor losses is important to successfully simulate high-speed serial link designs. The Huray model [1] is used in 3D full-wave solver and good correlation exists between measurement and simulation. Finally, current distribution of different layout design is also studied to reduce surface roughness effect.