Chi-Tsung Chiu

Novel Cu-to-Cu Bonding With Ti Passivation at 180

A novel CMOS-compatible bond structure using Cu-to-Cu bonding with Ti passivation is demonstrated at low temperature and investigated. With the Ti protection of inner Cu, Cu bonding temperature can be reduced to 180 °C. In addition, excellent electrical stability against humidity and temperature cycling is achieved. Diffusion behavior and mechanism of Cu and Ti are also discussed. With excellent bond results and reliability, this bonded scheme has the potential to be applied in 3-D integration.

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This paper presents a Through-Silicon-Via (TSV) based double-side integrated microsystem for brain neural sensing applications. Figure 6.3.1 shows the structure of the double-side integrated microsystem. MEMS neural microprobe array and low-power CMOS readout circuit are fabricated on two sides of the same silicon substrate, and TSVs are used to form a low impedance interconnection between the microprobe and CMOS circuitry, thus providing the shortest signal transmission distance from sensors to circuits. The low parasitic impedance of TSV minimizes transmission loss and noise. The overall chip is 5x5mm2, 350μm in thickness including 150μm probe height and 200μm TSV height, respectively. A total of 480 microprobes is divided into 4x4 sensing areas, forming 16channels. 16 TSV arrays are used to connect the microprobe outputs to 16 readout circuits fabricated on the opposite side of the silicon substrate. The proposed structure allows stacking of other CMOS chips onto the circuit side by TSV 3D IC technique.

in 3-D Integration

A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has six temperature sensitive ring oscillators (TSROs) generating frequency proportional to temperature. It dynamically selects the proper TSRO to convert the frequency into digital readings according to voltage status provided by PV sensors. With known process and voltage information from PV sensors, a pure temperature measurement result can be obtained. The proposed PVT sensors are designed in TSMC 65nm CMOS technology. This work can be dynamically operated over an ultra-low voltage range from 0.25V to 0.5V. Only 2.3μW is consumed at 0.25V. They can achieve 0.15 C resolution and 50k samples/sec conversion rate.

Through-silicon-via-based double-side integrated microsystem for neural sensing applications

Two bonded structures, Cu/In bonding and Cu-Cu bonding with Ti passivation, were investigated for the application of 3D interconnects. For Cu/In bonding, the bonds were achieved at 170°C due to the isothermal solidification. The intermetallic compounds formed in the joint was Cu2In phase. For another case, Cu-Cu bonding with Ti passivation was successfully achieved at 180°C Application of Ti passivation can protect inner Cu from oxidation; therefore, the required bonding temperature can be decreased. Compared to direct Cu-Cu bonding, Cu/In bonding and Cu-Cu bonding with Ti passivation can be performed at low temperature, which can meet low thermal budget requirement for most devices. Besides, with the good electrical performance and reliability, these two bonded interconnects can be applied for 3D IC interconnects.

Near-/Sub-V th process, voltage, and temperature (PVT) sensors with dynamic voltage selection

Low-temperature (170°C) Cu/In wafer-level and chip-level bonding for good thermal budget has been successfully developed for 3-D integration applications. For the well-bonded interconnect, Cu2In and Cu7In3 phases with high melting temperature of 388.3°C and 632.2°C can be formed, indicating high thermal stability. In addition, stable low specific contact resistance of bonded interfaces can be achieved with the values of approximately 0.3×10-8 Ω-cm2. In addition to exceptional electrical characteristics, the results of electrical reliability assessments including current stressing, temperature cycling, and unbiased HAST show excellent stability of Cu/In bonds without obvious deterioration. The low-temperature Cu/In bonding technology presents good bond quality and electrical performance, and possesses a great potential for future applications of 3-D interconnects.

Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration

We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18xa0μm CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5u2009×u20095xa0mm2 in area, with 16 channels of 150xa0μm-in-length neural probe array on the back-side, 200xa0μm-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5u2009×u20096 probe array, 3u2009×u200914 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8xa0V supply, 21.88xa0μW power consumption, 108xa0dB CMRR and 2.56 μVrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58xa0days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.

Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration

Heterogeneously integrated and miniaturized neural sensing microsystems for accurately capturing and classifying signals are crucial for brain function investigation and neural prostheses realization [1]. Many neural sensing microsystems have been proposed to provide small form-factor and biocompatible properties, including stacked multichip [2, 3], microsystem with separated neural sensors [4], monolithic packaged microsystem [5] and through-silicon-via (TSV) based double-side integrated microsystem [6]. These heterogeneous biomedical devices are composed of sensors and CMOS circuits for biopotential acquisition, signal processing and transmission. However, the weak signals detected from sensors in [2-5] have to pass through a string of interconnections to the CMOS circuits by wire bonding. In view of this, TSV-based double-side integration [6] uses TSV arrays to transfer the weak signals from μ-probe arrays to CMOS circuits for reducing noises. Nevertheless, the double-side integration requires preserving large area for separate μ-probe arrays and TSV arrays, and the TSV fabrication process may induce damage on CMOS circuits.

A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications

Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications

A low temperature bonding technology of Sn/In composite solder bonded to Cu interconnect is proposed and investigated. The intermetallic compounds formed in the bonded interconnects can survive well in the following process. The Sn/In-Cu interconnects bonded at low temperature all exhibit excellent electrical performance and high resistance to multiple current stressing, showing a great potential in 3D applications.

A TSV-Based Bio-Signal Package With

In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18μm CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6μW power consumption and 0.032-mm2 area. The FoM of this ADC is 49.4fJ/conversion-step.