Lih-Tyng Hwang

Thermal stress analysis of a multichip package design

The authors present a thermal analysis of a thin-film multichip package design, with emphasis on thermally induced stress in the critical package components. The package uses flip-chip solder bonding and thin-film interconnections between chips. Indium was chosen as the die attachment medium between each chip and the water-cooled heat sink. A methodology is given to estimate the stresses in the structure during a power-up. Finite-difference and finite-element computer simulations were used to calculate the temperature and stress distributions under both transient and steady-state conditions. It is shown how thermal gradients, expansion mismatches, and global bending of the structure determine the stress distribution. The components in the module have various thermal time constants, and the stresses during a transient are related to the rate at which each component heats up. For instance, the chips and the heat sink complete 70% of their temperature rise in the first 200 ms, but the substrate takes over 10 s to reach 70% of its steady-state temperature rise. Therefore, even if a design is optimized to be thermal expansion matched under operating conditions, stresses can develop during a transient. >

A review of the skin effect as applied to thin film interconnections

As the rise time of digital pulses is reduced to the subnanosecond range, the skin effect becomes an important issue in high-speed digital systems. The various approaches (theoretical and experimental) which have been taken to study the skin effect are surveyed. Various methods that accommodate the skin effect phenomenon into conductor design rules for high-speed digital systems are examined and compared. The resulting impact of these accommodations on high performance ULSI/VLSI multichip packages is addressed. >

Passivation schemes for copper/polymer thin film interconnections used in multichip modules

The use of thin inorganic dielectric films as barrier layers between copper and polyimide was examined. Emphasis was placed on discovering the effectiveness of the barrier layers in preventing copper/polyimide interaction and determining its impact on the high-frequency electrical performance of transmission line structures. The integrity of the inorganic dielectric layers as diffusion barriers for the copper was analyzed using transmission electron microscopy. These effects were studied by depositing thin layers of Si/sub 3/N/sub 4/, SiO/sub 2/, and SiO/sub x/N/sub y/ between chromium/copper/chromium lines and either Dow benzocyclobutene or Dupont 2525 polyimide. Both sputtered Si/sub 3/N/sub 4/ and PECVD SiO/sub x/N/sub y/ behaved as diffusion barriers, which resulted in improved performance at very high frequencies over unprotected transmission lines.<<ETX>>

Simulation and design of lossy transmission lines in a thin-film multichip package

A thin-film multichip package design was evaluated for its applications in packaging high-performance VLSI/ULSI chips. Typical thin-film interconnections (copper lines 8 mu m wide and 4 mu m thick) were analyzed, and a large CMOS driver was used in the simulation. It was found that a pitch of 32 mu m for the microstrip configuration and 20 mu m for the stripline configuration is required to obtain a low-crosstalk environment for an input frequency up to 1 GHz. It is shown that long lines (length between 8 cm and 18 cm) do not need any termination, but short lines (shorter than 8 cm, but longer than the length at which a line is considered to be a lumped circuit) must be terminated with customized termination resistors to obtain optimal package performance. The loading effects n the termination behavior of short and long thin-film microstrips are also discussed. It is shown that high power generation in thin-film lines at a high frequency (1 GHz) would require an advanced cooling technique for the thin-film multichip package. >

Calculation of electrical parameters of a thin-film multichip package

The calculations of the electrical parameters of a thin-film multichip package are presented. It is shown that a commonly used 2-D device simulator, PISCES, can be used to compute the electrical parameters of the thin-film lines up to a frequency where the skin effect is important. For trapezoidal conductor cross-sections, it is shown that the maximum variations of self- and mutual (coupling) capacitances are within 10% of their corresponding rectangular values when the sidewall angle of the conductor is varied up to 30 degrees , and the line cross-section area is kept constant. For the case when the conductor base is kept constant, the variation in mutual capacitance is found to be within 30% and that for self-capacitance is found to be within 12% when the sidewall angle is varied up to 30 degrees . A simple R-L-C circuit is used to represent a three-conductor lossy transmission line system, and SPICE is used to analyze the responses in the time domain. A thin-film multichip package design is briefly outlined. A HP-8510 network analyzer is used to verify the simulation results. >

Effects of polymer/metal interaction in thin-film multichip module applications

An investigation was conducted to examine the effects of different polyimide/metal combinations on structures similar to those used in thin-film multichip module applications. Three different metal structures and three commercially available spin-on polyimide materials which possess different molecular structures were examined. Transmission electron microscopy was used to study the polyimide/metal interfaces. Measurements of the transmission characteristics of line structures fabricated using the different metal/polyimide combinations were compared. It was found that the extent of interaction of polyimide with copper is dependent upon the type of polyimide used. Dupont 2611D polyimide showed the least amount of interaction with only a small band of precipitates present approximately 5 kAA from the copper/polyimide interface, which do not affect the electrical transmission characteristics of lines spaced 22 mu m a part. The use of an electrodes nickel layer on copper to retard copper/polyimide interaction from occurring during the curing cycle of the polyimide was found to be effective. However, increased loss of transmission at high frequencies and narrow spacing was seen for nickel-clad lines embedded in Dupont 2611D polyimide. Since nickel is a magnetic material, this increase in loss may be due to natural inductance from the nickel present in neighboring lines.<<ETX>>

Thermal analysis of a multi–chip package design

Two-dimensional finite difference computer simulations were used for thermal analysis of an advanced multi-chip package design. In order to model high performance VLSI and ULSI applications, power dissipations ranging from 10 to 40 W/cm2 on each chip and zero to 5 W/cm2 on the substrate were simulated. It was found that heating due to resistive losses in the thin film interconnections between chips can impact package thermal performance. The calculated device-to-water thermal resistance was 0.4° C/W and the worst case chip-to-chip temperature variation was less than 22° C. This excellent thermal performance illustrates the effectiveness of the package’s water cooled heat sink with direct backside contact to each die. Methods to improve thermal performance are discussed.

Calculation of voltage drops in the vias of a multichip package

A methodology for calculation of the voltage drops in the vias of a multichip package is presented. The vias are treated as lumped-circuit elements, and the excess capacitance and inductance of the vias are not considered. Numerical techniques were employed to determine the voltage and current waveforms of the signal path between two chips. After the current waveforms for the vias were determined, the voltage drop in ground was obtained by multiplying the current by the internal partial impedance. It was found that the peak noise is very small (in the range of 0.0005 V for a parallel-terminated line) for an input of 1 V due to the utilization of multiple power and ground vias in the design considered. it is point out that the location of the vias (relative to the drivers) has to be carefully chosen when the peak voltage drops are to be minimized.<<ETX>>

Skin effect in high-speed ULSI/VLSI packages

effect in high-speed ULSI/VLSI packagesLih-Tyng Hwang and Iwona TurlikCenter for Microelectronics, MCNCP.O. Box 12889, Research Triangle Park, NC 27709-2889ABSTRACTAs the rise time of digital pulses is reduced to the subnanosecond range, the skin effect becomes an important issue inhigh-speed digital systems. In this paper, the various approaches (theoretical and experimental) which have been taken tostudy the skin effect are surveyed. Various methods that accommodate the skin effect phenomenon into conductor designrules for high-speed digital systems are examined and compared. The resulting impact of these accommodations on high per-formance ULSI/VLSI multichip packages is addressed.

Design and process impact on thin-film interconnection performance

The performance of thin-film interconnections is influenced by the manner in which material selection and design rules interact with process capabilities. To understand this influence analysis of predicted and measured interconnection performance was correlated to design and process attributes. The models employed to predict propagation delay and noise are described and compared to experimental results. Attributes which contribute significantly to successful implementation of this technology are identified and accommodations in process controls and design rules are suggested.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.