Huo Zongliang

A novel 2-T structure memory device using a Si nanodot for embedded application

Performance and reliability of a 2 transistor Si nanocrystal nonvolatile memory (NVM) are investigated. A good performance of the memory cell has been achieved, including a fast program/erase (P/E) speed under low voltages, an excellent data retention (maintaining for 10 years) and good endurance with a less threshold voltage shift of less than 10% after 104 P/E cycles. The data show that the device has strong potential for future embedded NVM applications.

Comparison between N2 and O2 anneals on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack

In this paper the endurance characteristics and trap generation are investigated to study the effects of different post-deposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack. The flat-band voltage (Vfb) turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.

A simple and accurate method for measuring program/erase speed in a memory capacitor structure

With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

Investigation of charge loss characteristics of HfO2 annealed in N2 or O2 ambient

The retention characteristics of electrons and holes in hafnium oxide with post-deposition annealing in a N2 or O2 ambient were investigated by Kelvin probe force microscopy. The KFM results show that compared with the N2 PDA process, the O2 PDA process can lead to a significant retention improvement. Vertical charge leakage and lateral charge spreading both played an important role in the charge loss mechanisms. The retention improvement is attributed to the deeper trap energy. For electrons, the trap energy of the HOS structure annealed in a N2 or O2 ambient were determined to be about 0.44 and 0.49 eV, respectively. For holes, these are about 0.34 and 0.36 eV, respectively. Finally, the electrical characteristics of the memory devices are demonstrated from the experiment, which agreed with our characterization results. The qualitative and quantitative determination of the charge retention properties, the possible charge decay mechanism and trap energy reported in this work can be very useful for the characterization of hafnium charge storage devices.

Charge Loss Characteristics of Different Al Contents in a HfAlO Trapping Layer Investigated by Variable Temperature Kelvin Probe Force Microscopy

Kelvin probe force microscopy (KFM) technology is applied to investigate the charge storage and loss characteristics of the HfAlO charge trapping layer with various Al contents. The experimental results demonstrate that with the increase of Al contents in the HfAlO trapping layer, trap density significantly increases. Improvement of data retention characteristic is also observed. Comparing the vertical charge loss and lateral charge spreading of the HfAlO trapping layers, the former plays a major role in the charge loss mechanism. Variable temperature KFM measurement results show that the extracted effective electron trap energy level increases with increasing Al contents in HfAlO trapping layer, which is in accordance with the charge loss characteristics.

Material properties and effective work function of reactive sputtered TaN gate electrodes

The resistivity, crystalline structure and effective work function (EWF) of reactive sputtered TaN has been investigated. As-deposited TaN films have an fcc structure. After post-metal annealing (PMA) at 900 °C, the TaN films deposited with a N2 flow rate greater than 6.5 sccm keep their fcc structure, while the films deposited with a N2 flow rate lower than 6.25 sccm exhibit a microstructure change. The flatband voltages of gate stacks with TaN films as gate electrodes on SiO2 and HfO2 are also measured. It is concluded that a dipole is formed at the dielectric-TaN interface and its contribution to the EWF of TaN changes with the Ta/N ratio in TaN, the underneath dielectric layer and the PMA conditions.