Hwann-Kaeo Chiou

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm2. The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm2. The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm2. A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm2.

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We report a novel lumped element balun structure for both monolithic and hybrid circuit applications. The proposed structure utilizes two filters to compensate the amplitude and phase errors at the two balance outputs of a traditional out-of-phase power splitter. This circuit requires no multilayer or suspended substrates techniques; therefore, wide applications on many circuits operated especially, in the low microwave band, are expected. Two monolithic microwave integrated circuit (MMIC) mixers were built to demonstrate the electrical feasibility.

CMOS Technology

This work reports a novel lump-element balun for use in a miniature monolithic subharmonically pumped resistive mixer (SPRM) microwave monolithic integrated circuit. The proposed balun is simply analogous to the traditional Marchand balun. The coupled transmission lines are replaced by lump elements, significantly reducing the size of the balun. This balun requires no complicated three-dimensional electromagnetic simulations, multilayers or suspended substrate techniques; therefore, the design parameters are easily calculated. A 2.4-GHz balun is demonstrated using printed circuit board technology. The measurements show that the outputs of balun with high-pass and band-pass responses, a 1-dB gain balance, and a 5/spl deg/ phase balance from 1.7 to 2.45 GHz. The balun was then applied in the design of a 28-GHz monolithic SPRM. The measured conversion loss of the mixer was less than 11dB at a radio frequency (RF) bandwidth of 27.5-28.5 GHz at a fixed 1 GHz IF, a local oscillator (LO)-RF isolation of over 35 dB, and a 1-dB compression point higher than 9 dBm. The chip area of the mixer is less than 2.0 mm/sup 2/.

Lumped-element compensated high/low-pass balun design for MMIC double-balanced mixer

This paper proposes a high-efficiency dual-band on-chip rectifying antenna (rectenna) at 35 and 94 GHz for wireless power transmission. The rectenna is designed in slotline (SL) and finite-width ground coplanar waveguide (FGCPW) transmission lines in a CMOS 0.13-μm process. The rectenna comprises a high gain linear tapered slot antenna (LTSA), an FGCPW to SL transition, a bandpass filter, and a full-wave rectifier. The LTSA achieves a VSWR=2 fractional bandwidth of 82% and 41%, and a gain of 7.4 and 6.5 dBi at the frequencies of 35 and 94 GHz. The measured power conversion efficiencies are 53% and 37% in free space at 35 and 94 GHz, while the incident radiation power density is 30 mW/cm2 . The fabricated rectenna occupies a compact size of 2.9 mm2.

Compact 28-GHz subharmonically pumped resistive mixer MMIC using a lumped-element high-pass/band-pass balun

A V-band on-chip dipole-based antenna for 60 GHz wireless personal area network (WPAN) application is implemented using WIN 0.15 mum pHEMT process. The fabricated antenna has a compact size of 0.9 mm2, including test pads. The antenna comprises a half-wavelength dipole element and two tilted and slotted dipole elements to realize a wider impedance bandwidth than conventional wire dipole antennas, and provides endfire radiation patterns with high front-to-back ratio. The antenna performance is characterized using S-parameter, two-antenna (identical), three-antenna, and radiation pattern measurement methods for return loss, transmission gain, absolute gain, and radiation patterns. Measurement results shows that the on-chip antenna achieves a VSWR = 2 fractional bandwidth of 24% (55 to 70 GHz), a transmission gain of - 32 dB (the separated distance R = 5 cm), an absolute gain of 3.6 dBi, a front-to-back ratio of 12 dB, and an half-power beamwidth of 60deg in E-plane and H-plane. The measured and simulated results are shown in good agreements.

High-Efficiency Dual-Band On-Chip Rectenna for 35- and 94-GHz Wireless Power Transmission in 0.13-

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively.

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This paper presents symmetric offset stack Marchand single and dual baluns that are designed, analyzed, and implemented in a 0.18-μm CMOS process to verify the feasibility. Both single and dual baluns achieve measured bandwidths (BWs) of over 110% and 90%, and insertion losses of less than 4.4 and 7.4 dB at 38 GHz. The amplitude imbalance and phase imbalance of single and dual baluns are less than 1 dB and 5° from 10 to 67 and 11 to 50 GHz, respectively. The baluns were used in three broadband balanced passive mixers, i.e., a single-balanced resistive mixer (SBRM), a star mixer, and a subharmonic gate pumped resistive mixer (SHPRM) design in a 0.13-μm CMOS technology. These mixers exhibit wide BWs over 14-45 GHz (105%), 18-54 GHz (100%), and 28-50 GHz (56%). The 14-45-GHz SBRM achieves a conversion loss of better than 12 dB at 7 dBm of local oscillator (LO) power. The LO to RF and LO to IF isolations are better than 30 dB. The chip area is 0.53 mm2. The star mixer achieves a conversion loss of better than 12 dB from 18 to 54 GHz, and LO to RF, LO to IF, and RF to IF isolations better than 35 dB at LO frequencies spanning 10-60 GHz. The chip area is 0.6 mm2. The SHPRM has a conversion loss of better than 11 dB from 28 to 50 GHz. The isolations are better than 31 dB and occupy a chip area of 0.61 mm2.

CMOS Technology

This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

V-Band On-Chip Dipole-Based Antenna

We report generation of high-modulation-depth photonic millimeter-wave (MMW) waveforms by applying line-by-line pulse shaping on a phase-modulated continuous-wave frequency comb. The optimized 20 and 100 GHz optical waveforms are then converted into electrical MMW signals using a near-ballistic uni-traveling-carrier photodiode (NBUTC-PD). A 7.4 dB MMW power enhancement is experimentally achieved by using 2.6 ps optimized pulses at a 100 GHz repetition rate, as compared with excitation by a conventional sinusoidal signal for the NBUTC-PD operated at the same photocurrent. This is in qualitative agreement with a theoretical analysis of spectral power enhancement by optical short pulses comprised of equi-amplitude frequency lines over sinusoidal excitation.

A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver

This brief proposes a third-order active notch filter for an interferer-rejection (IR) ultrawideband low-noise amplifier (LNA) in a 0.18-μm complementary metal-oxide-semiconductor process. The design formulas are derived by considering the minimum power dissipation for the active notch filter that provides proper selections of the device size, the bias conditions, and the values of LC resonator. The active notch filter was then incorporated into a wideband common-gate LNA as an IR-LNA. The measurements show that the IR-LNA achieves a maximum gain of 14.7 dB, a minimum noise figure of 5.3 dB, an IR ratio of 35.7 dB, and an input third-order intercept point of -2.5 dBm at a 16-mW power dissipation, while the active notch filter rejects the interfering signal at 5.8 GHz. The chip area is 0.51 mm2, including testing pads.